公开(公告)号：US20140299919A1

公开(公告)日：2014-10-09

申请号：US14354648

申请日：2012-07-31

申请人： Haizhou Yin ,  Wei Jiang ,  Huilong Zhu

发明人： Haizhou Yin ,  Wei Jiang ,  Huilong Zhu

IPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A semiconductor device and a method for manufacturing the same are provided. In one embodiment, the method comprises: growing a first epitaxial layer on a substrate; forming a sacrificial gate stack on the first epitaxial layer; selectively etching the first epitaxial layer; growing and in-situ doping a second epitaxial layer on the substrate; forming a spacer on opposite sides of the sacrificial gate stack; and forming source/drain regions with the spacer as a mask.

摘要翻译： 提供半导体器件及其制造方法。 在一个实施例中，该方法包括：在衬底上生长第一外延层; 在所述第一外延层上形成牺牲栅叠层; 选择性地蚀刻第一外延层; 在衬底上生长并原位掺杂第二外延层; 在所述牺牲栅极堆叠的相对侧上形成间隔物; 以及用间隔物形成源极/漏极区域作为掩模。

公开(公告)号：US20140287565A1

公开(公告)日：2014-09-25

申请号：US14354894

申请日：2011-12-02

申请人： Haizhou Yin ,  Weize Yu

发明人： Haizhou Yin ,  Weize Yu

IPC分类号： H01L29/66

CPC分类号： H01L29/66545 ,  H01L21/28 ,  H01L29/66575 ,  H01L29/78

摘要： The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) providing a substrate (100); b) forming a dummy gate stack on the substrate (100), wherein the dummy gate stack consists of a gate dielectric layer (203) and a dummy gate (201) located on the gate dielectric layer (203), and the material of the dummy gate (201) is amorphous Si; c) performing ion implantation to regions exposed on both sides of the dummy gate (201) on the substrate (100), so as to form source/drain regions (110); d) forming an interlayer dielectric layer (400) that covers the source/drain regions (110) and the dummy gate stack; e) removing part of the interlayer dielectric layer (400) to expose the dummy gate (201) and removing the dummy gate (201); and f) annealing to activate dopants in source/drain regions. Procedures of the traditional gate-replacement process have been modified by the method for manufacturing a semiconductor structure provided by the present invention, thus etching period can be easily controlled, etching difficulty is alleviated, and stability of etching process is guaranteed as well.

摘要翻译： 本发明提供一种制造半导体结构的方法，其包括：a）提供衬底（100）; b）在所述衬底（100）上形成虚拟栅极堆叠，其中所述虚设栅极叠层由位于所述栅极介电层（203）上的栅极介电层（203）和伪栅极（201）组成， 伪栅极（201）是非晶Si; c）对在衬底（100）上的伪栅极（201）的两侧露出的区域进行离子注入，以形成源/漏区（110）; d）形成覆盖源极/漏极区域（110）和虚拟栅极叠层的层间电介质层（400） e）去除所述层间介电层（400）的一部分以暴露所述虚拟栅极（201）并去除所述伪栅极（201）; 和f）退火以激活源/漏区中的掺杂剂。 已经通过本发明提供的半导体结构的制造方法改进了传统的栅极替换工艺，因此可以容易地控制蚀刻时间，减轻蚀刻难度，并且保证蚀刻工艺的稳定性。

公开(公告)号：US08815698B2

公开(公告)日：2014-08-26

申请号：US13381636

申请日：2011-07-26

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L27/04 ,  H01L21/76 ,  H01L21/8238 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/66651

摘要： A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to fill the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to fill the grooves.

摘要翻译： 提供了半导体技术领域中的阱区形成方法和半导体基底。 一种方法包括：在半导体衬底中形成隔离区以隔离有源区; 选择所述有源区域中的至少一个，以及在所选择的有源区域中形成第一阱区域; 形成掩模以覆盖所选择的有源区，并蚀刻其余的有源区，以便形成沟槽; 并通过外延生长半导体材料以填充凹槽。 另一种方法包括：在半导体衬底中形成用于隔离有源区的隔离区; 在活跃区域形成井区; 蚀刻有源区以形成凹槽，使得凹槽具有小于或等于阱区深度的深度; 并通过外延生长半导体材料以填充凹槽。

公开(公告)号：US20140197410A1

公开(公告)日：2014-07-17

申请号：US13697096

申请日：2012-05-17

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/04

CPC分类号： H01L29/78 ,  H01L21/76283 ,  H01L29/04 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

摘要： The present invention provides a method for manufacturing a semiconductor structure. The method comprises: providing an SOI substrate and forming a gate structure on said SOI substrate; etching a SOI layer and a BOX layer of the SOI substrate on both sides of the gate structure to form a trench exposing the BOX layer, said trench partially entering into the BOX layer; forming a stressed layer that fills up a part of said trench; forming a semiconductor layer covering the stressed layer in the trench. Correspondingly, the present invention also provides a semiconductor structure formed by the above method. In the semiconductor structure and the method for manufacturing the same according to the present invention, a trench is formed on an ultrathin SOI substrate, first filled with a stressed layer, and then filled with a semiconductor material to be ready for forming a source/drain region. The stressed layer provides a favorable stress to the channel of the semiconductor device, thus facilitating improving the performance of the semiconductor device.

摘要翻译： 本发明提供一种半导体结构的制造方法。 该方法包括：提供SOI衬底并在所述SOI衬底上形成栅极结构; 在栅极结构的两侧蚀刻SOI衬底的SOI层和BOX层，以形成露出BOX层的沟槽，所述沟槽部分地进入BOX层; 形成填充所述沟槽的一部分的应力层; 形成覆盖沟槽中的应力层的半导体层。 相应地，本发明还提供了通过上述方法形成的半导体结构。 在根据本发明的半导体结构及其制造方法中，在超薄SOI衬底上形成沟槽，首先填充有应力层，然后填充半导体材料以准备形成源极/漏极 地区。 应力层对半导体器件的通道提供有利的应力，从而有助于提高半导体器件的性能。

公开(公告)号：US08729661B2

公开(公告)日：2014-05-20

申请号：US13379533

申请日：2011-04-25

申请人： Zhijiong Luo ,  Haizhou Yin ,  Huilong Zhu

发明人： Zhijiong Luo ,  Haizhou Yin ,  Huilong Zhu

IPC分类号： H01L21/70

CPC分类号： H01L21/02647 ,  H01L21/02639 ,  H01L21/76229

摘要： A semiconductor structure and a method for manufacturing the same are disclosed. The method comprises: disposing a first dielectric material layer on a first semiconductor layer and defining openings in the first dielectric material layer; epitaxially growing a second semiconductor layer on the first semiconductor layer via the openings defined in the first dielectric material layer, wherein the second semiconductor layer and the first semiconductor layer comprise different materials from each other; and forming plugs of a second dielectric material in the second semiconductor layer at positions where the openings are defined in the first dielectric material layer and also at middle positions between adjacent openings. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed.

摘要翻译： 公开了一种半导体结构及其制造方法。 该方法包括：在第一半导体层上设置第一介电材料层并在第一介电材料层中限定开口; 通过限定在第一介电材料层中的开口在第一半导体层上外延生长第二半导体层，其中第二半导体层和第一半导体层包括彼此不同的材料; 以及在所述第二半导体层中形成所述第一介电材料层中所述开口的位置以及在相邻开口之间的中间位置处形成第二电介质材料的插塞。 根据本公开的实施例，可以有效地抑制在异质外延生长期间发生的缺陷。

公开(公告)号：US08729638B2

公开(公告)日：2014-05-20

申请号：US13696071

申请日：2011-11-30

申请人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7856 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

摘要： A method for making FinFETs and semiconductor structures formed therefrom is disclosed, comprising: providing a SiGe layer on a Si semiconductor substrate and a Si layer on the SiGe layer, wherein the lattice constant of the SiGe layer matches that of the substrate; patterning the Si layer and the SiGe layer to form a Fin structure; forming a gate stack on top and both sides of the Fin structure and a spacer surrounding the gate stack; removing a portion of the Si layer which is outside the spacer with the spacer as a mask, while keeping a portion of the Si layer which is inside the spacer; removing a portion of the SiGe layer which is kept after the patterning, to form a void; forming an insulator in the void; and epitaxially growing stressed source and drain regions on both sides of the Fin structure and the insulator.

摘要翻译： 公开了一种用于制造FinFET和由其形成的半导体结构的方法，包括：在Si半导体衬底上提供SiGe层和SiGe层上的Si层，其中SiGe层的晶格常数与衬底的晶格常数相匹配; 图案化Si层和SiGe层以形成Fin结构; 在Fin结构的顶部和两侧上形成栅极堆叠以及围绕栅极堆叠的间隔物; 在间隔物作为掩模的同时，除去间隔物外部的Si层的一部分，同时保持间隔物内部的Si层的一部分; 去除在图案化之后保留的SiGe层的一部分，以形成空隙; 在空隙中形成绝缘体; 并在鳍结构和绝缘体的两侧外延生长应力源极和漏极区。

公开(公告)号：US08710556B2

公开(公告)日：2014-04-29

申请号：US12937652

申请日：2010-06-25

申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Qiagqing Liang

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Qiagqing Liang

IPC分类号： H01L29/76 ,  H01L27/12 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

摘要： The present application discloses a semiconductor device comprising a fin of semiconductive material formed from a semiconductor layer over a semiconductor substrate and having two opposing sides perpendicular to the main surface of the semiconductor substrate; a source region and a drain region provided in the semiconductor substrate adjacent to two ends of the fin and being bridged by the fin; a channel region provided at the central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, and wherein the stack of gate dielectric and gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the semiconductor substrate, and insulated from the semiconductor substrate by an insulating layer. The semiconductor device has an improved short channel effect and a reduced parasitic capacitance and resistance, which contributes to an improved electrical property and facilitates scaling down of the transistor.

摘要翻译： 本申请公开了一种半导体器件，其包括由半导体衬底上的半导体层形成并具有垂直于半导体衬底的主表面的两个相对侧的半导体材料的鳍; 源极区域和漏极区域，设置在所述半导体衬底中，邻近所述鳍片的两端并被所述鳍片桥接; 设置在所述翅片的中央部的通道区域; 以及设置在鳍的一侧的栅极电介质和栅极导体的堆叠，其中栅极导体通过栅极电介质与沟道区隔离，并且其中栅极电介质和栅极导体的堆叠远离 翅片在平行于半导体衬底的主表面的方向上，并且通过绝缘层与半导体衬底绝缘。 半导体器件具有改善的短沟道效应和减小的寄生电容和电阻，这有助于改善电性能并且有助于晶体管的缩小。

公开(公告)号：US08658507B2

公开(公告)日：2014-02-25

申请号：US12990714

申请日：2010-06-24

申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Qingqing Liang

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Qingqing Liang

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L29/1054 ,  H01L29/66583 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7834 ,  H01L29/7848

摘要： There is provided a MOSFET structure and a method of fabricating the same. The method includes: providing a semiconductor substrate; forming a dummy gate on the semiconductor substrate; forming source/drain regions; selectively etching the dummy gate to a position where a channel is to be formed; and epitaxially growing a channel layer at the position where the channel is to be formed and forming a gate on the channel layer, wherein the channel layer comprises a material of high mobility. Thereby, the channel of the device is replaced with the material of high mobility after the source/drain region is formed, and thus it is possible to suppress the short channel effect and also to improve the device performance.

摘要翻译： 提供了一种MOSFET结构及其制造方法。 该方法包括：提供半导体衬底; 在半导体衬底上形成虚拟栅极; 形成源/漏区; 选择性地将伪栅极蚀刻到要形成沟道的位置; 并且在通道的位置上外延生长沟道层，并在沟道层上形成栅极，其中沟道层包括高迁移率的材料。 因此，在形成源极/漏极区域之后，器件的沟道被高迁移率的材料代替，从而可以抑制短沟道效应并且还能够提高器件性能。

公开(公告)号：US20130307034A1

公开(公告)日：2013-11-21

申请号：US13640735

申请日：2012-05-17

申请人： Haizhou Yin ,  Wei Jiang

发明人： Haizhou Yin ,  Wei Jiang

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： A method of manufacturing a semiconductor structure, which comprises the steps of: providing a substrate, forming a fin on the substrate, which comprises a central portion for forming a channel and an end portion for forming a source/drain region and a source/drain extension region; forming a gate stack to cover the central portion of the fin; performing light doping to form a source/drain extension region in the end portion of the fin; forming a spacer on sidewalls of the gate stack; performing heavy doping to form a source/drain region in the end portion of the fin; removing at least a part of the spacer to expose at least a part of the source/drain extension region; forming a contact layer on an upper surface of the source/drain region and an exposed area of the source/drain extension region. Correspondingly, the present invention also provides a semiconductor structure. By forming a thin contact layer in the source/drain extension region, the present invention can not only effectively reduce the contact resistance of the source/drain extension region, but also effectively control the junction depth of the source/drain extension region by controlling the thickness of the contact layer, thereby suppressing the short channel effect.

摘要翻译： 一种制造半导体结构的方法，包括以下步骤：提供衬底，在衬底上形成翅片，其包括用于形成沟道的中心部分和用于形成源极/漏极区域的端部和源极/漏极 延伸区域 形成栅极堆叠以覆盖鳍片的中心部分; 执行轻掺杂以在鳍的端部形成源/漏延伸区; 在所述栅极堆叠的侧壁上形成间隔物; 进行重掺杂以在鳍的端部形成源/漏区; 去除所述间隔物的至少一部分以暴露所述源极/漏极延伸区域的至少一部分; 在源极/漏极区域的上表面和源极/漏极延伸区域的暴露区域上形成接触层。 相应地，本发明还提供一种半导体结构。 通过在源极/漏极延伸区域中形成薄的接触层，本发明不仅可以有效地降低源极/漏极延伸区域的接触电阻，而且可以通过控制源极/漏极延伸区域的结深度来有效地控制源极/漏极延伸区域的结深度 接触层的厚度，从而抑制短沟道效应。

公开(公告)号：US20130277768A1

公开(公告)日：2013-10-24

申请号：US13816228

申请日：2011-12-01

申请人： Haizhou Yin ,  Weize Yu

发明人： Haizhou Yin ,  Weize Yu

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L21/28176 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66553 ,  H01L29/66575 ,  H01L29/78

摘要： The present invention provides a semiconductor structure and a method for manufacturing the same. The method comprises the following steps: providing a substrate and forming a sacrificial gate, sidewall spacers and source/drain regions located on both sides of the sacrificial gate; forming an interlayer dielectric layer that covers the device; removing the sacrificial gate to form a cavity within the sidewall spacers; forming first oxygen absorbing layers in the cavity; forming a second oxygen absorbing layer in the remaining of the space of the cavity; and performing an annealing step to make the surface of the substrate form an interfacial layer. The present invention further provides a semiconductor structure. By forming a symmetrical interfacial layer in a channel region, the present invention has reduced processing difficulty while effectively mitigating short-channel effects and preserving carrier mobility.

摘要翻译： 本发明提供半导体结构及其制造方法。 该方法包括以下步骤：提供衬底并形成位于牺牲栅极两侧的牺牲栅极，侧壁间隔物和源极/漏极区域; 形成覆盖所述器件的层间电介质层; 去除所述牺牲栅极以在所述侧壁间隔件内形成空腔; 在空腔中形成第一氧吸收层; 在空腔的剩余部分中形成第二氧吸收层; 并进行退火步骤以使基材的表面形成界面层。 本发明还提供一种半导体结构。 通过在通道区域中形成对称的界面层，本发明降低了处理难度，同时有效地减轻了短沟道效应并保持了载流子迁移率。