公开(公告)号：US08085588B2

公开(公告)日：2011-12-27

申请号：US12433084

申请日：2009-04-30

申请人： Naoharu Shinozaki ,  Kenji Arai ,  Satoshi Sakurakawa

发明人： Naoharu Shinozaki ,  Kenji Arai ,  Satoshi Sakurakawa

IPC分类号： G11C16/04

CPC分类号： G11C8/12 ,  G11C16/08

摘要： Systems and methods for programming data to a memory device (MD). The methods involve receiving the data at MD (100) from an external data source. MD includes a memory cell array (MCA) for storing the data including numbers in data blocks (DB) or memory cell array planes (MCAP). Each DB (122a, 122b, 122c, 122d) and MCAP (1020a, 1020b, 1020c, 1020d) includes memory addresses (Ads) corresponding to locations of respective transistor circuits (2021, 2022, . . . , 202n, . . . , 202m) within the MCA (120, 1020a, 1020b, 1020c, 1020d). Two or more of the transistor circuits have different threshold voltages (TVs) with respect to each other. The methods further involve programming the data to each DB or MCAP in accordance with a first mode. In the first mode, each number is programmed to a different MA of each DB or MCAP based at least in part on the different TVs.

摘要翻译： 用于将数据编程到存储器件（MD）的系统和方法。 该方法涉及从外部数据源接收MD（100）的数据。 MD包括用于存储包括数据块（DB）或存储单元阵列平面（MCAP）中的数字的数据的存储单元阵列（MCA）。 每个DB（122a，122b，122c，122d）和MCAP（1020a，1020b，1020c，1020d）包括对应于各个晶体管电路（2021,2022，...，202n，...）的位置的存储器地址（Ads） 202m）在MCA（120,1020a，1020b，1020c，1020d）内。 两个或多个晶体管电路相对于彼此具有不同的阈值电压（TV）。 所述方法还包括根据第一模式将数据编程到每个DB或MCAP。 在第一模式中，至少部分地基于不同的电视机将每个数字编程到每个数据块或MCAP的不同MA。

公开(公告)号：US07969816B2

公开(公告)日：2011-06-28

申请号：US12548034

申请日：2009-08-26

申请人： Naoharu Shinozaki ,  Satoshi Moue

发明人： Naoharu Shinozaki ,  Satoshi Moue

IPC分类号： G11C8/16

CPC分类号： G11C7/22 ,  G11C7/10

摘要： Systems and methods for reading data from or writing data to a memory device. The methods involve receiving a first pulse signal having a first pulse frequency at the memory device. The methods also involve generating, at the memory device, a second pulse signal using the first pulse signal. The second pulse signal is a compliment of the first pulse signal. The second pulse signal has a second pulse frequency that is equal to the first frequency. The fist pulse signal is used to control first read/write operations so that first data is output from or input to the memory device at a first data rate. The first and second pulse signals are used to control second read/write operations so that second data is output from or input to the memory device at a second data rate. The second data rate is twice the first data rate.

摘要翻译： 用于从存储器件读取数据或将数据写入存储器件的系统和方法。 所述方法包括在存储器件处接收具有第一脉冲频率的第一脉冲信号。 该方法还涉及在存储器件中使用第一脉冲信号产生第二脉冲信号。 第二脉冲信号是第一脉冲信号的补充。 第二脉冲信号具有等于第一频率的第二脉冲频率。 第一脉冲信号用于控制第一读/写操作，使得第一数据以第一数据速率从存储器件输出或输入到存储器件。 第一和第二脉冲信号用于控制第二读/写操作，使得第二数据以第二数据速率从存储器件输出或输入到存储器件。 第二个数据速率是第一个数据速率的两倍。

公开(公告)号：US20060285413A1

公开(公告)日：2006-12-21

申请号：US11508917

申请日：2006-08-24

申请人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

发明人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

IPC分类号： G11C7/00

CPC分类号： G11C29/028 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C29/02 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/0403 ,  G11C2211/4061

摘要： A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.

公开(公告)号：US06963518B2

公开(公告)日：2005-11-08

申请号：US10387398

申请日：2003-03-14

申请人： Junichi Sasaki ,  Naoharu Shinozaki

发明人： Junichi Sasaki ,  Naoharu Shinozaki

IPC分类号： G11C11/407 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C8/00

CPC分类号： G11C7/103 ,  G11C7/1048 ,  G11C7/22 ,  G11C2207/002

摘要： A pulse generator generates a plurality of column pulses in response to a read command. An address counter outputs addresses subsequent to an external address supplied in association with the read command in succession as internal addresses. A column decoder successively selects column selecting lines in synchronization with the column pulses. A plurality of bits of data read from memory cells in response to a single read command RD is successively transmitted to a common data bus line through column switches. This can reduce the number of data bus lines to a minimum, preventing an increase in chip size. Since a single data bus line can transmit a plurality of bits of data, it is possible to minimize the size of the memory region to be activated in response to a read command. This consequently allows a reduction in power consumption.

摘要翻译： 脉冲发生器响应于读取命令产生多个列脉冲。 地址计数器作为内部地址连续地输出与读取命令相关联地提供的外部地址之后的地址。 列解码器与列脉冲同步地连续地选择列选择线。 响应于单个读取命令RD从存储器单元读取的多个数据位被连续地通过列开关发送到公共数据总线。 这可以将数据总线的数量减少到最小，防止芯片尺寸的增加。 由于单个数据总线能够发送多个数据位，所以可以根据读取命令最小化要激活的存储器区域的大小。 因此，能够降低功耗。

公开(公告)号：US06333875B1

公开(公告)日：2001-12-25

申请号：US09666586

申请日：2000-09-20

申请人： Naoharu Shinozaki

发明人： Naoharu Shinozaki

IPC分类号： G11C700

CPC分类号： G11C7/109 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/4076 ,  G11C11/4093

摘要： A semiconductor circuit which receives a strobe signal and a data signal includes a latch-signal-generation circuit which generates a first latch signal delayed by a first delay time relative to the strobe signal and a second latch signal inverted and delayed by a second delay time relative to the strobe signal, a control circuit which adaptively controls the latch-signal-generation circuit to adjust timings of the first and second latch signals such that the first delay time and the second delay time become substantially equal, and a latch circuit which latches the data signal at edge timings of the first and second latch signals.

摘要翻译： 接收选通信号和数据信号的半导体电路包括锁存信号产生电路，其产生延迟相对于选通信号的第一延迟时间的第一锁存信号，以及反相并延迟第二延迟时间的第二锁存信号 相对于所述选通信号，控制电路，其自适应地控制所述锁存信号产生电路，以调整所述第一和第二锁存信号的定时，使得所述第一延迟时间和所述第二延迟时间变得基本相等;以及锁存电路， 在第一和第二锁存信号的边沿定时处的数据信号。

公开(公告)号：US06330682B1

公开(公告)日：2001-12-11

申请号：US09104374

申请日：1998-06-25

申请人： Kazuyuki Kanazashi ,  Naoharu Shinozaki ,  Toshiya Uchida

发明人： Kazuyuki Kanazashi ,  Naoharu Shinozaki ,  Toshiya Uchida

IPC分类号： G06F104

CPC分类号： G11C8/18

摘要： A semiconductor memory device having an internal circuit includes a command decoder which decodes input-command signals to supply decoded-command signals, an address-latch-signal-generation circuit, operating faster than the command decoder, which decodes the input-command signals to supply an address-latch signal, and a control circuit which controls the internal circuit based on the decoded-command signals. The semiconductor memory device further includes an address-input circuit which latches an address signal in response to the address-latch signal.

摘要翻译： 具有内部电路的半导体存储器件包括命令解码器，其对输入命令信号进行解码以提供解码命令信号，地址锁存信号产生电路比命令解码器运行得更快，将输入命令信号解码为 提供地址锁存信号，以及基于解码指令信号控制内部电路的控制电路。 半导体存储器件还包括地址输入电路，其响应于地址锁存信号而锁存地址信号。

公开(公告)号：US06288928B1

公开(公告)日：2001-09-11

申请号：US09588230

申请日：2000-06-06

申请人： Naoharu Shinozaki

发明人： Naoharu Shinozaki

IPC分类号： G11C506

CPC分类号： G11C7/1072 ,  G11C11/4076 ,  G11C11/4091

摘要： A semiconductor integrated circuit comprising a memory cell, a column switch for transmitting data to a bit line, a sense amplifier for amplifying data, a precharging circuit for charging the bit line, and a control unit. The control unit controls the transfer switch in the memory cell, the column switch, the sense amplifier, and the precharging circuit so as to differentiate the control timings of these circuits between a write operation and a read operation. For example, the column switch is turned on after the transfer switch is turned on and before the amplification of the sense amplifier is started in a write operation. Here, the data retained in the memory cell are rewritten into write data before amplified by the sense amplifier. This minimizes the data inversion time and heightens the speed of write operations. The power consumption can be reduced since the circuits optimally operate in accordance with the operating modes.

摘要翻译： 一种半导体集成电路，包括存储单元，用于向位线发送数据的列开关，用于放大数据的读出放大器，用于对位线充电的预充电电路以及控制单元。 控制单元控制存储单元，列开关，读出放大器和预充电电路中的转换开关，以便在写入操作和读取操作之间区分这些电路的控制定时。 例如，在转换开关接通之后并且在写入操作中开始读出放大器的放大之前，列开关被接通。 这里，保持在存储单元中的数据在被读出放大器放大之前被重写为写入数据。 这最小化数据反转时间并提高写入操作的速度。 由于电路根据工作模式进行最佳的操作，所以能够降低功耗。

公开(公告)号：US06288585B1

公开(公告)日：2001-09-11

申请号：US09535745

申请日：2000-03-27

申请人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita ,  Kota Hara ,  Naoharu Shinozaki

发明人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita ,  Kota Hara ,  Naoharu Shinozaki

IPC分类号： H03L706

CPC分类号： H03L7/0805 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

摘要： A semiconductor device receiving a stable external power voltage includes a reduced-voltage-generation circuit which generates an internally reduced power voltage, an input circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.

摘要翻译： 接收稳定的外部电源电压的半导体器件包括产生内部降低的电源电压的降压产生电路，基于内部降低的电源电压进行操作的输入电路，使内部降低的电源电压波动， 控制电路，其产生内部时钟信号;输出电路，其响应于内部时钟信号以输出定时将数据信号输出到设备的外部;时钟传送电路，其传送来自时钟控制电路的内部时钟信号 到输出电路，并且基于外部电源电压进行操作，以使得输出定时基本上不受内部降低的功率电压的波动的影响。

公开(公告)号：US6166973A

公开(公告)日：2000-12-26

申请号：US365508

申请日：1999-08-02

申请人： Naoharu Shinozaki

发明人： Naoharu Shinozaki

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/842 ,  G11C7/1039

摘要： The present invention is a memory device having a multiple-bit data pre-fetch function wherein the operation of a redundancy checking circuit for comparing addresses and redundant addresses and checking the coincidence or non-coincidence thereof is started with timing prior to performing the last data fetches. The address signals are supplied with the same timing as the supply of the write commands, wherefore it is not always necessary for the operation of comparing the address signals against the redundant addresses of the memory cells, where the switch to the redundant cell array was performed, to have to wait until all of the multiple-bit data to be fetched. Accordingly, with the present invention, the redundancy checking operation is started before all of the data are fetched. In the case of a 2-bit data pre-fetch, the redundancy checking operation is started after the first datum has been fetched, and before the second bit of data is fetched. That being so, it is possible to begin the decoder operation with timing that is faster by precisely the period of the redundancy checking operation, wherefore it becomes possible to perform write operations to the memory cells with faster timing.

摘要翻译： 本发明是具有多位数据预取功能的存储器件，其中用于比较地址和冗余地址的冗余校验电路的操作以及检查其一致性或不一致性是在执行最后数据之前的定时开始的 提取 以与写入命令的供给相同的时序提供地址信号，因此对于将地址信号与存储器单元的冗余地址进行比较的操作并不总是必需的，其中执行到冗余单元阵列的切换 ，必须等待所有的多位数据被提取。 因此，利用本发明，在获取所有数据之前开始冗余校验操作。 在2位数据预取的情况下，在获取第一数据之后并且在获取第二位数据之前开始冗余校验操作。 就这样，可以通过精确地进行冗余校验操作的周期的时间更快地开始解码器操作，因此可以以更快的定时对存储器单元执行写入操作。

公开(公告)号：US5994886A

公开(公告)日：1999-11-30

申请号：US926463

申请日：1997-09-10

申请人： Naoharu Shinozaki

发明人： Naoharu Shinozaki

IPC分类号： G11C11/413 ,  G05F1/46 ,  G05F5/08 ,  G11C11/401 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04

CPC分类号： G05F1/465

摘要： An internal step-down power supply circuit for lowering an external power supply voltage supplied from outside to an internal power supply voltage in a semiconductor device includes a circuit for generating the internal power supply voltage in response to a control voltage, potential regulation circuits for a normal operation and for a test operation, respectively, having fuse elements for making it possible to regulate the potential of the control circuit, and potential control circuits disposed for the normal operation and for the test operation, respectively, for controlling the potential of the control voltage on the basis of the output of the corresponding potential regulation circuit. The external power supply voltage is used as a power supply of the potential regulation circuit for the normal operation and the internal power supply voltage is used as a power supply of the potential regulation circuit for the test operation. This circuit construction can reduce a DC path current in a fuse circuit for regulating the potential of the internal step-down voltage power supply voltage and can provide low power consumption and stable operations.

摘要翻译： 一种用于将从外部供应的外部电源电压降低到半导体器件中的内部电源电压的内部降压电源电路包括：用于响应于控制电压产生内部电源电压的电路，用于 分别具有用于调节控制电路的电位的熔丝元件和用于正常操作和测试操作的电位控制电路的正常操作和测试操作，用于控制控制电位 电压基于相应电位调节电路的输出。 外部电源电压用作正常工作的电位调节电路的电源，内部电源电压用作用于测试操作的电位调节电路的电源。 该电路结构可以减小熔丝电路中的DC路径电流，以调节内部降压电压电压的电位，并且可以提供低功耗和稳定的操作。