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    Semiconductor device using external power voltage for timing sensitive signals
    1.
    发明授权
    Semiconductor device using external power voltage for timing sensitive signals 有权
    半导体器件使用外部电源电压进行时序敏感信号

    公开(公告)号：US06288585B1

    公开(公告)日：2001-09-11

    申请号：US09535745

    申请日：2000-03-27

    申请人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita ,  Kota Hara ,  Naoharu Shinozaki

    发明人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita ,  Kota Hara ,  Naoharu Shinozaki

    IPC分类号： H03L706

    CPC分类号： H03L7/0805 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

    摘要： A semiconductor device receiving a stable external power voltage includes a reduced-voltage-generation circuit which generates an internally reduced power voltage, an input circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.

    摘要翻译： 接收稳定的外部电源电压的半导体器件包括产生内部降低的电源电压的降压产生电路，基于内部降低的电源电压进行操作的输入电路，使内部降低的电源电压波动， 控制电路，其产生内部时钟信号;输出电路，其响应于内部时钟信号以输出定时将数据信号输出到设备的外部;时钟传送电路，其传送来自时钟控制电路的内部时钟信号 到输出电路，并且基于外部电源电压进行操作，以使得输出定时基本上不受内部降低的功率电压的波动的影响。

    Semiconductor integrated circuit device
    2.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US06318707B1

    公开(公告)日：2001-11-20

    申请号：US09536467

    申请日：2000-03-28

    申请人： Kota Hara ,  Hiroyoshi Tomita ,  Naoharu Shinozaki

    发明人： Kota Hara ,  Hiroyoshi Tomita ,  Naoharu Shinozaki

    IPC分类号： G11C800

    CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/22 ,  G11C7/225

    摘要： A semiconductor integrated circuit device includes a clock buffer circuit receiving a clock signal, a data buffer circuit receiving a data signal, an output circuit outputting the data signal from the data buffer circuit in accordance with the clock signal from the clock buffer circuit, and an adjustment circuit adjusting timings of the clock signal and the data signals.

    摘要翻译： 一种半导体集成电路装置，包括接收时钟信号的时钟缓冲电路，接收数据信号的数据缓冲电路，根据来自时钟缓冲器电路的时钟信号从数据缓冲电路输出数据信号的输出电路，以及 调整电路调整时钟信号和数据信号的定时。

    SEMICONDUCTOR MEMORY DEVICE WITH REDUCED CURRENT CONSUMPTION
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE WITH REDUCED CURRENT CONSUMPTION 失效
    具有降低电流消耗的半导体存储器件

    公开(公告)号：US20090092000A1

    公开(公告)日：2009-04-09

    申请号：US12146962

    申请日：2008-06-26

    申请人： Kota Hara

    发明人： Kota Hara

    IPC分类号： G11C8/10

    CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C11/406 ,  G11C11/4085 ,  G11C11/4087 ,  G11C2211/4067 ,  G11C2211/4068

    摘要： A semiconductor memory device includes memory blocks, a main word decoder to set a main word line to a first potential for activation, a second potential, or a third potential, a circuit to generate a cyclic signal that indicates timing at intervals, a block selecting circuit to select a memory block to be accessed, a successive-selection circuit to select the memory blocks one after another, and a circuit configured to control the main word decoder such that unselected ones of the main word lines of a memory block selected by the block selecting circuit are set to the third potential, such that the main word lines of the selected memory block are maintained at the third potential after access, and such that the main word lines of a memory block selected by the successive-selection circuit are set to the second potential at the timing indicated by the cyclic signal.

    摘要翻译： 半导体存储器件包括存储块，将主字线设置为第一电位用于激活的主字解码器，第二电位或第三电位的电路，用于产生以间隔指示定时的循环信号的电路，块选择 选择要访问的存储器块的电路，连续选择电路，用于依次选择存储器块;以及电路，被配置为控制主字解码器，使得由所述存储器块选择的未选择的主字线 块选择电路被设置为第三电位，使得所选择的存储块的主字线在访问之后保持在第三电位，并且使得由连续选择电路选择的存储块的主字线被设置 在由循环信号指示的定时处于第二电位。

    Magnetic recording disk and process for manufacture thereof
    5.
    发明授权
    Magnetic recording disk and process for manufacture thereof 有权
    磁记录盘及其制造方法

    公开(公告)号：US07277254B2

    公开(公告)日：2007-10-02

    申请号：US11097283

    申请日：2005-04-04

    申请人： Koichi Shimokawa ,  Kota Hara

    发明人： Koichi Shimokawa ,  Kota Hara

    IPC分类号： G11B5/127 ,  G11B5/725

    CPC分类号： G11B5/725 ,  G11B5/8408

    摘要： A magnetic recording disk having a substrate, a magnetic layer formed on the substrate, a protective layer formed on the magnetic layer and a lubricant layer formed on the protective layer, the lubricant layer containing a perfluoropolyether compound having an end moiety containing a phosphazene ring and a perfluoropolyether compound having an end moiety containing a hydroxyl group, or the lubricant layer containing a perfluoropolyether compound having an end moiety containing a hydroxyl group on the protective layer side and a perfluoropolyether compound having an end moiety containing a phosphazene ring on the other surface side, and a process for manufacturing each of these magnetic recording disks.

    摘要翻译： 一种磁记录盘，其具有基板，形成在基板上的磁性层，形成在磁性层上的保护层和形成在保护层上的润滑层，润滑层含有具有含有磷腈环的末端部分的全氟聚醚化合物和 具有包含羟基的末端部分的全氟聚醚化合物，或含有在保护层侧具有羟基的末端部分的全氟聚醚化合物的润滑剂层和在另一个表面侧具有含有磷腈环的末端部分的全氟聚醚化合物 ，以及这些磁记录盘的制造方法。

    Semiconductor memory
    6.
    发明授权
    Semiconductor memory 有权

    公开(公告)号：US06621750B2

    公开(公告)日：2003-09-16

    申请号：US10155029

    申请日：2002-05-28

    申请人： Yoshiaki Okuyama ,  Shinya Fujioka ,  Kota Hara ,  Katsuhiro Mori

    发明人： Yoshiaki Okuyama ,  Shinya Fujioka ,  Kota Hara ,  Katsuhiro Mori

    IPC分类号： G11C700

    CPC分类号： G11C29/808 ,  G11C29/812 ,  G11C29/848

    摘要： A redundancy memory circuit stores a defect address indicating a defective memory cell row. A redundancy control circuit disables the defective memory cell row corresponding to the defect address stored in the redundancy memory circuit and enables a redundancy memory cell row in the memory block containing the defective memory cell row. Moreover, in the other memory blocks, the redundancy control circuit disables memory cell rows corresponding to the defective memory cell row and enables redundancy memory cell rows instead of these memory cell rows. Consequently, not only the memory block having the defective memory cell row but one of the memory cell rows in the other memory blocks is always also relieved. Thus, the redundancy memory circuit can be shared among all the memory blocks with a reduction in the number of redundancy memory circuits. As a result, the semiconductor memory can be reduced in chip size.

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US07254090B2

    公开(公告)日：2007-08-07

    申请号：US11340471

    申请日：2006-01-27

    申请人： Kota Hara ,  Akira Kikutake

    发明人： Kota Hara ,  Akira Kikutake

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1027 ,  G11C11/4076 ,  G11C2207/002

    摘要： An internal address generating circuit sequentially generates internal addresses in the burst read operation, with an external address being set as an initial value. A memory core has plural memory cells and sequentially outputs, in response to activation of a column selection signal, data read from the memory cells corresponding to the internal addresses in the burst read operation. In the burst read operation, a column control circuit in a memory core control circuit repeats activation of the column selection signal for a certain period during an activation period of an external control signal and forcibly deactivates the column selection signal in synchronization with deactivation of the external control signal. In the burst read operation, an operation state control circuit in the memory core control circuit deactivates an operation state control signal after a predetermined time has elapsed from the deactivation of the external control signal.

    Memory circuit having compressed testing function
    9.
    发明授权
    Memory circuit having compressed testing function 有权
    存储电路具有压缩测试功能

    公开(公告)号：US06731553B2

    公开(公告)日：2004-05-04

    申请号：US10270196

    申请日：2002-10-15

    申请人： Shinya Fujioka ,  Waichiro Fujieda ,  Kota Hara

    发明人： Shinya Fujioka ,  Waichiro Fujieda ,  Kota Hara

    IPC分类号： G11C700

    CPC分类号： G11C29/40

    摘要： A multi-bit output configuration memory circuit comprises: a memory core having a normal cell array and a redundant cell array, which have a plurality of memory cells; N output terminals which respectively output N-bit output read out from the memory core; an output circuit provided between the output terminals and the memory core, which detects whether each L-bit output of the N-bit output (N=L×M) read out from said memory core matches or not and outputs a compressed output which becomes the output data in the event of a match while becomes a third state in the event of a non-match, to a first output terminal of the N output terminals. Responding to each of a plurality of test commands or the test control signals of the external terminals, the compressed output of the M groups of L-bit output is outputted in time shared.

    摘要翻译： 多比特输出配置存储器电路包括：具有正常单元阵列的存储器核心和具有多个存储单元的冗余单元阵列; N个输出端子，分别输出从存储器芯读出的N位输出; 输出电路，设置在输出端子和存储器核心之间，其检测从所述存储器芯片读出的N位输出（N = L×M）的每个L位输出是否匹配，并输出成为输出的压缩输出 在匹配的情况下的数据在不匹配的情况下变为第三状态时，输出到N个输出端的第一输出端。 响应多个测试命令或外部终端的测试控制信号中的每一个，M个组的L位输出的压缩输出以时间共享的形式被输出。

    Semiconductor storage device and memory system
    10.
    发明授权
    Semiconductor storage device and memory system 有权
    半导体存储设备和存储系统

    公开(公告)号：US08724425B2

    公开(公告)日：2014-05-13

    申请号：US13398495

    申请日：2012-02-16

    申请人： Kota Hara

    发明人： Kota Hara

    IPC分类号： G11C8/00

    CPC分类号： G11C8/10 ,  G11C8/06 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4082

    摘要： A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal.

    摘要翻译： 一种半导体存储装置，包括提供第一信号的外部端子，核心电路以及访问操作控制电路，其基于第一信号的脉冲宽度生成指示到核心电路的接入操作模式的信号，用于后续周期 信号。