公开(公告)号：US06288585B1

公开(公告)日：2001-09-11

申请号：US09535745

申请日：2000-03-27

申请人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita ,  Kota Hara ,  Naoharu Shinozaki

发明人： Yoshihide Bando ,  Nobutaka Taniguchi ,  Hiroyoshi Tomita ,  Kota Hara ,  Naoharu Shinozaki

IPC分类号： H03L706

CPC分类号： H03L7/0805 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

摘要： A semiconductor device receiving a stable external power voltage includes a reduced-voltage-generation circuit which generates an internally reduced power voltage, an input circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.

摘要翻译： 接收稳定的外部电源电压的半导体器件包括产生内部降低的电源电压的降压产生电路，基于内部降低的电源电压进行操作的输入电路，使内部降低的电源电压波动， 控制电路，其产生内部时钟信号;输出电路，其响应于内部时钟信号以输出定时将数据信号输出到设备的外部;时钟传送电路，其传送来自时钟控制电路的内部时钟信号 到输出电路，并且基于外部电源电压进行操作，以使得输出定时基本上不受内部降低的功率电压的波动的影响。

公开(公告)号：US06318707B1

公开(公告)日：2001-11-20

申请号：US09536467

申请日：2000-03-28

申请人： Kota Hara ,  Hiroyoshi Tomita ,  Naoharu Shinozaki

发明人： Kota Hara ,  Hiroyoshi Tomita ,  Naoharu Shinozaki

IPC分类号： G11C800

CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/22 ,  G11C7/225

摘要： A semiconductor integrated circuit device includes a clock buffer circuit receiving a clock signal, a data buffer circuit receiving a data signal, an output circuit outputting the data signal from the data buffer circuit in accordance with the clock signal from the clock buffer circuit, and an adjustment circuit adjusting timings of the clock signal and the data signals.

摘要翻译： 一种半导体集成电路装置，包括接收时钟信号的时钟缓冲电路，接收数据信号的数据缓冲电路，根据来自时钟缓冲器电路的时钟信号从数据缓冲电路输出数据信号的输出电路，以及 调整电路调整时钟信号和数据信号的定时。

公开(公告)号：US06522182B2

公开(公告)日：2003-02-18

申请号：US09385008

申请日：1999-08-27

申请人： Hiroyoshi Tomita ,  Naoharu Shinozaki ,  Nobutaka Taniguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Kenichi Kawasaki ,  Masafumi Yamazaki ,  Kazuhiro Ninomiya

发明人： Hiroyoshi Tomita ,  Naoharu Shinozaki ,  Nobutaka Taniguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Kenichi Kawasaki ,  Masafumi Yamazaki ,  Kazuhiro Ninomiya

IPC分类号： H03L706

CPC分类号： H03L7/0805 ,  G11C7/1072 ,  G11C7/222 ,  H03K5/131

摘要： In the present invention, an external power source supplied to an integrated circuit device is divided into a first external power source for the DLL circuit and a second external power source for circuits other than the DLL circuit. According to the present invention, it is arranged that power source noise generated in the second external power source cannot be transmitted to the variable delay circuit by utilizing the first external power source preferably for the variable delay circuit of the DLL circuit and even more preferably for its delay unit. Also, preferably, it is arranged that power source noise generated in the second external power source cannot be transmitted to the phase coincidence detection unit by utilizing the first power source for the phase coincidence detection unit in the phase comparison circuit of the DLL circuit. Also, by connecting the first external earthing power source to the variable delay circuit and/or phase coincidence detection unit, the effect of power source noise from the second external earthing power source originating from the operation of circuits other than these is suppressed.

摘要翻译： 在本发明中，提供给集成电路装置的外部电源被分成用于DLL电路的第一外部电源和除了DLL电路以外的电路的第二外部电源。 根据本发明，通过利用第一外部电源优选用于DLL电路的可变延迟电路，而将第二外部电源中产生的电源噪声不能传输到可变延迟电路，甚至更优选地用于 其延迟单位。 此外，优选地，通过利用DLL电路的相位比较电路中的相位一致检测单元的第一电源，将第二外部电源中产生的电源噪声不能发送到相位一致检测单元。 此外，通过将第一外部接地电源连接到可变延迟电路和/或相位一致检测单元，抑制源于除了这些以外的电路的操作的来自第二外部接地电源的电源噪声的影响。

公开(公告)号：US06339353B1

公开(公告)日：2002-01-15

申请号：US09542454

申请日：2000-04-04

申请人： Hiroyoshi Tomita ,  Naoharu Shinozaki

发明人： Hiroyoshi Tomita ,  Naoharu Shinozaki

IPC分类号： H03K3356

CPC分类号： G11C7/109 ,  G11C8/06 ,  H03K3/012 ,  H03K3/356121 ,  H03K3/356139 ,  H03K5/133 ,  H03K5/1534

摘要： The present invention provides an input circuit having small current consumption in a clock synchronization type semiconductor integrated circuit. The input circuit is activated by an activation signal to receive an input signal and an activation signal generating circuit generates the activation signal. The activation signal generating circuit activates intermittently the activation signal for a time shorter than a period of a clock signal and including a setup time and a hold time of the input signal in order to activate the input circuit. The input circuit is activated only for the limited time of one period of the clock signal and therefore current consumption can be reduced.

摘要翻译： 本发明提供一种在时钟同步型半导体集成电路中具有小电流消耗的输入电路。 输入电路由激活信号激活以接收输入信号，激活信号产生电路产生激活信号。 激活信号发生电路间歇地激活比时钟信号周期短的时间的激活信号，并且包括输入信号的建立时间和保持时间，以激活输入电路。 输入电路仅在时钟信号的一个周期的有限时间内被激活，因此可以减少电流消耗。

公开(公告)号：US06317372B1

公开(公告)日：2001-11-13

申请号：US09528983

申请日：2000-03-20

申请人： Tomonori Hayashi ,  Naoharu Shinozaki ,  Hiroyoshi Tomita

发明人： Tomonori Hayashi ,  Naoharu Shinozaki ,  Hiroyoshi Tomita

IPC分类号： G11C2900

CPC分类号： G11C29/40 ,  G11C29/34 ,  G11C29/48

摘要： An input conversion unit converts serial data supplied from the exterior into parallel data. Each of the converted parallel data is respectively written into a plurality of memory cell areas. An output conversion unit converts parallel data constructed by data read from each memory cell area into serial data. An operational unit is activated during a testing mode so as to logically operate on the parallel data read from each memory cell area. By writing predetermined data into each memory cell area in advance, it is confirmed by a logic operation that correct data is stored in each memory cell area. The data can be checked simultaneously for the plurality of memory cell areas so that the operation test in the memory cell areas can be carried out at high speed. Besides, serial data accepted, twice per cycle of a data strobe signal, is converted into parallel data. Each of the converted parallel data is respectively written into a first memory cell area and a second memory cell area. Parallel data read from the first and second memory cell area is logically operated in a testing mode and the operation result is output at once in synchronization with the clock signal. Accordingly, the data can be checked simultaneously for the first and the second memory cell area so that the operation test in the memory cell areas can be carried out at high speed.

摘要翻译： 输入转换单元将从外部提供的串行数据转换为并行数据。 每个转换的并行数据分别写入多个存储单元区域。 输出转换单元将从每个存储单元区域读取的数据构成的并行数据转换为串行数据。 在测试模式期间激活操作单元，以便对从每个存储单元区域读取的并行数据进行逻辑运算。 通过预先将预定数据写入每个存储单元区域，通过逻辑运算来确认正确的数据被存储在每个存储单元区域中。 可以同时检查多个存储单元区域的数据，使得可以高速地执行存储单元区域中的操作测试。 此外，接受数据选通信号每周期两次的串行数据被转换为并行数据。 每个转换的并行数据分别被写入第一存储器单元区域和第二存储器单元区域中。 从第一和第二存储单元区域读取的并行数据在测试模式下逻辑运行，并且与时钟信号同步地一次输出运算结果。 因此，可以同时检查第一和第二存储单元区域的数据，使得可以高速地执行存储单元区域中的操作测试。

公开(公告)号：US06307806B1

公开(公告)日：2001-10-23

申请号：US09652162

申请日：2000-08-31

申请人： Hiroyoshi Tomita ,  Naoharu Shinozaki

发明人： Hiroyoshi Tomita ,  Naoharu Shinozaki

IPC分类号： G11C800

CPC分类号： G11C7/1018 ,  G11C8/18 ,  G11C11/4082 ,  G11C29/78

摘要： A command receiving circuit receives a command signal for determining a circuit operation, in synchronization with a clock signal and it outputs the received command signal as an internal command signal. An address switching circuit permits transmission of an address signal to an internal circuit upon receiving the command signal. The internal circuit receives the address signal before the reception of the command signal, thereby to start its operation. As a result, the internal circuit can be operated at high speed. Besides, the address switching circuit inhibits the transmission of the address signal to the internal circuit upon receiving the internal command signal or the clock signal. Therefore, even when the level of the address signal has changed after the reception of the command signal, the change does not lead to operating the internal circuit. Accordingly, the power consumption of the semiconductor integrated circuit is reduced. Meanwhile, the semiconductor integrated circuit comprises a plurality of memory cores and a bank switch for selecting the memory cores. The bank switch feeds the address signal to predetermined memory core(s) of the memory cores in accordance with the value of the address signal. Since the memory core can receive the address signal before the validation of a command, the circuit operation is performed at high speed even in the semiconductor integrated circuit including the plurality of memory cores are controlled as bank.

摘要翻译： 命令接收电路与时钟信号同步地接收用于确定电路操作的命令信号，并且将所接收的命令信号作为内部命令信号输出。 地址切换电路允许在接收到命令信号时将地址信号发送到内部电路。 内部电路在接收到命令信号之前接收地址信号，从而开始其操作。 因此，内部电路可以高速运转。 此外，地址切换电路在接收到内部命令信号或时钟信号时，禁止向内部电路发送地址信号。 因此，即使在接收到指令信号之后地址信号的电平变化，也不会导致内部电路的工作。 因此，半导体集成电路的功耗降低。 同时，半导体集成电路包括多个存储器核和用于选择存储器核的组开关。 存储体交换机根据地址信号的值将存储器核心的地址信号提供给预定的存储器核心。 由于存储核心可以在命令验证之前接收地址信号，所以即使在包括多个存储器核心的半导体集成电路被控制为存储体的情况下，电路操作也以高速执行。

公开(公告)号：US08064264B2

公开(公告)日：2011-11-22

申请号：US11974295

申请日：2007-10-11

申请人： Naoharu Shinozaki ,  Masao Taguchi ,  Akira Ogawa ,  Takuo Ito

发明人： Naoharu Shinozaki ,  Masao Taguchi ,  Akira Ogawa ,  Takuo Ito

IPC分类号： G11C16/06

CPC分类号： G11C16/26

摘要： A semiconductor device that includes: a memory cell array that includes non-volatile memory cells; an area that is contained in the memory cell array and stores area data; a first storage unit that holds data transferred from the memory cell array, and outputs the data; and a control circuit that selects between a primary reading mode for causing the first storage unit to hold the area data transferred from the memory cell array and to output the area data, and a secondary reading mode for causing the first storage unit to hold a plurality of pieces of divisional data formed by dividing the area data and transferred from the memory cell array and to output the divisional data.

摘要翻译： 一种半导体器件，包括：包括非易失性存储单元的存储单元阵列; 包含在存储单元阵列中并存储区域数据的区域; 第一存储单元，保存从存储单元阵列传送的数据，并输出数据; 以及控制电路，其选择用于使所述第一存储单元保持从所述存储单元阵列传送的区域数据并输出所述区域数据的主读取模式;以及辅助读取模式，用于使所述第一存储单元保持多个 通过划分区域数据并从存储单元阵列传送而形成的分割数据并输出分割数据。

公开(公告)号：US07471585B2

公开(公告)日：2008-12-30

申请号：US11508917

申请日：2006-08-24

申请人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

发明人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

IPC分类号： G11C7/00

CPC分类号： G11C29/028 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C29/02 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/0403 ,  G11C2211/4061

摘要： A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.

摘要翻译： 响应于以预定周期产生的刷新请求输出刷新信号，并执行刷新操作。 刷新操作在访问请求与刷新请求之间发生冲突时结束。 因此，与访问请求相对应的访问操作可以随着访问时间的减少而更早地启动。 可以根据访问请求的提供时间改变刷新操作的结束时间，进一步减少访问时间。 由于形成用于将刷新操作的状态通知给外部的测试电路，因此可以在短时间内评估刷新操作的操作余量。 结果，可以减少半导体存储器的显影周期。

公开(公告)号：US07113441B2

公开(公告)日：2006-09-26

申请号：US11057841

申请日：2005-02-15

申请人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

发明人： Naoharu Shinozaki ,  Tatsuya Kanda ,  Takahiko Sato ,  Akihiro Funyu

IPC分类号： G11C7/00

CPC分类号： G11C29/028 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C29/02 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/0403 ,  G11C2211/4061

摘要： A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.

摘要翻译： 响应于以预定周期产生的刷新请求输出刷新信号，并执行刷新操作。 刷新操作在访问请求与刷新请求之间发生冲突时结束。 因此，与访问请求相对应的访问操作可以随着访问时间的减少而更早地启动。 可以根据访问请求的提供时间改变刷新操作的结束时间，进一步减少访问时间。 由于形成用于将刷新操作的状态通知给外部的测试电路，因此可以在短时间内评估刷新操作的操作余量。 结果，可以减少半导体存储器的显影周期。

公开(公告)号：US06438667B1

公开(公告)日：2002-08-20

申请号：US09236338

申请日：1999-01-25

申请人： Naoharu Shinozaki

发明人： Naoharu Shinozaki

IPC分类号： G06F1214

CPC分类号： G11C29/1201 ,  G11C29/48 ,  G11C2029/2602

摘要： When a test instruction signal is outputted from a command decoder, a test mode decoder receives the test instruction signal and outputs a test signal. When a DQM switch circuit receives the test signal, the DQM switch circuit outputs a mask/disable signal (MASK0 or MASK1) inputted to any one of two mask/disable terminals (DQML, DQMU) as a mask/disable signal inputted from the two terminals DQML and DQMU to a write amplifier/sense buffer. Therefore, it is possible to execute a mask/disable operation for all of input and output data with one of the two mask/disable terminals.

摘要翻译： 当从命令解码器输出测试指令信号时，测试模式解码器接收测试指令信号并输出​​测试信号。 当DQM开关电路接收到测试信号时，DQM开关电路输出输入到两个屏蔽/禁止端子（DQML，DQMU）中的任何一个的屏蔽/禁止信号（MASK0或MASK1）作为从两个输入端口输入的屏蔽/禁止信号 端子DQML和DQMU到写入放大器/检测缓冲器。 因此，可以通过两个屏蔽/禁止端子之一对所有的输入和输出数据执行掩码/禁止操作。