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1.发明授权Semiconductor device using external power voltage for timing sensitive signals 有权半导体器件使用外部电源电压进行时序敏感信号公开(公告)号：US06288585B1
公开(公告)日：2001-09-11
申请号：US09535745
申请日：2000-03-27
IPC分类号： H03L706
CPC分类号： H03L7/0805 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C7/222 , H03L7/0812
摘要： A semiconductor device receiving a stable external power voltage includes a reduced-voltage-generation circuit which generates an internally reduced power voltage, an input circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.
摘要翻译： 接收稳定的外部电源电压的半导体器件包括产生内部降低的电源电压的降压产生电路，基于内部降低的电源电压进行操作的输入电路，使内部降低的电源电压波动， 控制电路，其产生内部时钟信号;输出电路，其响应于内部时钟信号以输出定时将数据信号输出到设备的外部;时钟传送电路，其传送来自时钟控制电路的内部时钟信号 到输出电路，并且基于外部电源电压进行操作，以使得输出定时基本上不受内部降低的功率电压的波动的影响。
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公开(公告)号：US06522182B2
公开(公告)日：2003-02-18
申请号：US09385008
申请日：1999-08-27
申请人： Hiroyoshi Tomita , Naoharu Shinozaki , Nobutaka Taniguchi , Waichirou Fujieda , Yasuharu Sato , Kenichi Kawasaki , Masafumi Yamazaki , Kazuhiro Ninomiya
发明人： Hiroyoshi Tomita , Naoharu Shinozaki , Nobutaka Taniguchi , Waichirou Fujieda , Yasuharu Sato , Kenichi Kawasaki , Masafumi Yamazaki , Kazuhiro Ninomiya
IPC分类号： H03L706
CPC分类号： H03L7/0805 , G11C7/1072 , G11C7/222 , H03K5/131
摘要： In the present invention, an external power source supplied to an integrated circuit device is divided into a first external power source for the DLL circuit and a second external power source for circuits other than the DLL circuit. According to the present invention, it is arranged that power source noise generated in the second external power source cannot be transmitted to the variable delay circuit by utilizing the first external power source preferably for the variable delay circuit of the DLL circuit and even more preferably for its delay unit. Also, preferably, it is arranged that power source noise generated in the second external power source cannot be transmitted to the phase coincidence detection unit by utilizing the first power source for the phase coincidence detection unit in the phase comparison circuit of the DLL circuit. Also, by connecting the first external earthing power source to the variable delay circuit and/or phase coincidence detection unit, the effect of power source noise from the second external earthing power source originating from the operation of circuits other than these is suppressed.
摘要翻译： 在本发明中，提供给集成电路装置的外部电源被分成用于DLL电路的第一外部电源和除了DLL电路以外的电路的第二外部电源。 根据本发明，通过利用第一外部电源优选用于DLL电路的可变延迟电路，而将第二外部电源中产生的电源噪声不能传输到可变延迟电路，甚至更优选地用于 其延迟单位。 此外，优选地，通过利用DLL电路的相位比较电路中的相位一致检测单元的第一电源，将第二外部电源中产生的电源噪声不能发送到相位一致检测单元。 此外，通过将第一外部接地电源连接到可变延迟电路和/或相位一致检测单元，抑制源于除了这些以外的电路的操作的来自第二外部接地电源的电源噪声的影响。
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公开(公告)号：US6031788A
公开(公告)日：2000-02-29
申请号：US207335
申请日：1998-12-08
IPC分类号： G11C11/407 , G06F1/04 , G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1072
摘要： A semiconductor integrated circuit is adapted to make invalid an external clock, externally supplied to the semiconductor integrated circuit, when the semiconductor integrated circuit is set in an active power-down state. The semiconductor integrated circuit includes a delay locked loop DLL circuit which outputs an internal clock which phase is synchronized to the external clock. A latch circuit retains control signals in synchronism with the internal clock output by the DLL circuit. An internal circuit performs a predetermined process based on the control signals supplied from the latch circuit.
摘要翻译： 当半导体集成电路处于有功掉电状态时，半导体集成电路适于使外部提供给半导体集成电路的外部时钟无效。 半导体集成电路包括延迟锁定环DLL电路，其输出与外部时钟同步的内部时钟。 锁存电路保持与DLL电路的内部时钟输出同步的控制信号。 内部电路基于从锁存电路提供的控制信号执行预定处理。
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公开(公告)号：US06225843B1
公开(公告)日：2001-05-01
申请号：US09385005
申请日：1999-08-27
IPC分类号： H03L700
CPC分类号： H03L7/0805 , G11C7/22 , G11C7/222 , H03L7/0814 , H03L7/089
摘要： A semiconductor integrated circuit device includes a first delay circuit delaying a first clock signal, a second delay circuit delaying a second clock signal which has an inverted phase with respect to the first clock signal, a phase comparator outputting a phase error signal based on a comparison of the first clock signal and a feedback signal corresponding to an output signal from the first delay circuit, a delay control circuit generating a delay control signal based on the phase error signal, for variably controlling a delay quantity of the first and second delay circuits, and a timing adjusting circuit variably controlling a delay quantity of the second delay circuit by supplying the delay control signal to the second delay circuit at a timing synchronized to the second clock signal.
摘要翻译： 半导体集成电路器件包括延迟第一时钟信号的第一延迟电路，延迟相对于第一时钟信号具有反相的第二时钟信号的第二延迟电路;基于比较器输出相位误差信号的相位比较器 所述第一时钟信号和对应于来自所述第一延迟电路的输出信号的反馈信号，延迟控制电路，基于所述相位误差信号产生延迟控制信号，用于可变地控制所述第一和第二延迟电路的延迟量， 以及定时调整电路，通过在与第二时钟信号同步的定时向第二延迟电路提供延迟控制信号，可变地控制第二延迟电路的延迟量。
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公开(公告)号：US06242954B1
公开(公告)日：2001-06-05
申请号：US09385010
申请日：1999-08-27
IPC分类号： H04L708
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/0818 , H03L7/087
摘要： The present invention has a hierarchical DLL circuit comprising a rough DLL circuit for phase adjustment by rough delay unit and a fine DLL circuit for phase adjustment by smaller, fine delay unit. When phase adjustment begins, only the rough DLL circuit operates; when the rough DLL circuit locks on, phase adjustment by the rough DLL circuit ends and the delay amount of the rough DLL circuit is set. When the rough DLL circuit locks on, the fine DLL circuit is caused to operate. In this way, the phase of the timing clock generated by the DLL circuit is adjusted only by fine delay units even if the phase of the reference clock is temporarily shifted by a large amount due to power source noise or the like. Consequently, in the event of temporary phase shifting, the amount of jitter in the timing clock can be suppressed to the small amount of a fine delay unit. Phase adjustment by the rough DLL circuit is stopped by ending phase comparison by the phase comparison circuit, or ending the input of the clock to the phase comparison circuit, for example.
摘要翻译： 本发明具有分级DLL电路，其包括用于通过粗略延迟单元进行相位调整的粗略DLL电路和用于通过较小的精细延迟单元进行相位调整的精细DLL电路。 当相位调整开始时，只有粗略的DLL电路运行; 当粗体DLL电路锁定时，粗体DLL电路的相位调整结束，并设置粗略电路的延迟量。 当粗体DLL电路锁定时，使细小的DLL电路工作。 以这种方式，即使由于电源噪声等而使参考时钟的相位暂时移位了大量，由DLL电路产生的定时时钟的相位仅被微调延迟单元调整。 因此，在临时相移的情况下，可以将定时时钟中的抖动量抑制到微小的延迟单元的量。 例如，通过由相位比较电路结束相位比较或将时钟的输入结束到相位比较电路来停止粗略DLL电路的相位调整。
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公开(公告)号：US06194932B1
公开(公告)日：2001-02-27
申请号：US09383015
申请日：1999-08-25
IPC分类号： H03L700
CPC分类号： G11C7/222 , G06F1/10 , G11C7/22 , H03L7/0814
摘要： The present invention omits a variable delay circuit (10 in FIG. 1) inside a DLL circuit, and instead, creates a timing synchronization circuit, which generates a second reference clock. The timing synchronization circuit shifts the phase of a first reference clock generated by a frequency divider to the timing of a timing signal generated from the other variable delay circuit so that the second reference clock matches to the timing signal. Then, a phase comparator compares the divided first reference clock to a variable clock that delays the second reference clock, and controls the delay time of the variable delay circuit so that both clocks are in phase. As a result, one variable delay circuit can be omitted, and a DLL circuit that uses a divided clock can be configured.
摘要翻译： 本发明省略了DLL电路内部的可变延迟电路（图1中的10），而是产生产生第二参考时钟的定时同步电路。 定时同步电路将由分频器产生的第一参考时钟的相位移位到从另一个可变延迟电路产生的定时信号的定时，使得第二参考时钟与定时信号相匹配。 然后，相位比较器将分频的第一参考时钟与延迟第二参考时钟的可变时钟进行比较，并且控制可变延迟电路的延迟时间，使得两个时钟同相。 结果，可以省略一个可变延迟电路，并且可以配置使用分频时钟的DLL电路。
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公开(公告)号：US06181174B2
公开(公告)日：2001-01-30
申请号：US09404221
申请日：1999-09-23
IPC分类号： H03L706
CPC分类号： H03L7/0805 , G06F1/08 , G06F1/10 , G11C7/1039 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , H03K5/133 , H03K23/58 , H03L7/0814
摘要： A semiconductor integrated circuit device includes a DLL circuit. The DLL circuit includes a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clock and thus results in a dummy clock and a reference clock. A delay system includes a variable delay circuit which delays the dummy clock. A control circuit controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.
摘要翻译： 半导体集成电路装置包括DLL电路。 DLL电路包括分频器，该分频器以分频比对输入时钟进行分频，该分频比根据输入时钟的频率而变化，从而产生虚拟时钟和参考时钟。 延迟系统包括延迟虚拟时钟的可变延迟电路。 控制电路控制可变延迟电路的延迟量，使得来自延迟系统和参考时钟的延迟的虚拟时钟的相位变为零。
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8.发明授权Semiconductor device having timing-stabilization circuit and method of testing such semiconductor device 失效具有时序稳定电路的半导体器件和测试这种半导体器件的方法
公开(公告)号：US6108793A
公开(公告)日：2000-08-22
申请号：US40288
申请日：1998-03-18
CPC分类号： H03L7/0805 , G01R31/3016 , G06F1/04 , H03L7/0814 , H03L7/087 , H03L7/095
摘要： A method of measuring a time which a timing-stabilization circuit requires in order to complete timing stabilization with regard to a semiconductor device provided with a first function to reset the timing-stabilization circuit and a second function to output a signal indicative of completion of the timing stabilization is disclosed. The method includes the steps of a) activating the timing-stabilization circuit, b) detecting a timing of the completion of the timing stabilization by using the second function, and c) measuring the time which the timing-stabilization circuit requires to complete the timing stabilization based on the timing.
摘要翻译： 一种测量定时稳定电路所需的时间的方法，以便对具有第一功能的半导体器件完成定时稳定以复位定时稳定电路，以及第二功能，以输出指示完成的信号 公开了定时稳定。 该方法包括以下步骤：a）激活定时稳定电路，b）通过使用第二功能来检测定时稳定的定时，以及c）测量定时稳定电路完成定时所需的时间 基于时间稳定。
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公开(公告)号：US5901101A
公开(公告)日：1999-05-04
申请号：US919505
申请日：1997-08-28
申请人： Takaaki Suzuki , Masao Nakano , Hiroyoshi Tomita , Yasuharu Sato , Kotoku Sato , Nobutaka Taniguchi
发明人： Takaaki Suzuki , Masao Nakano , Hiroyoshi Tomita , Yasuharu Sato , Kotoku Sato , Nobutaka Taniguchi
IPC分类号： G11C11/403 , G11C11/406 , G11C11/407 , G11C7/00
CPC分类号： G11C11/406
摘要： In a semiconductor memory device operable in synchronism with a clock signal externally supplied thereto, there are provided a first part which detects a state of a predetermined signal after a given command is input to the semiconductor memory; and a second part which sets, on the basis of the state of the predetermined signal, the semiconductor memory device to a self-refresh mode in which a refresh operation is carried out without an external signal.
摘要翻译： 在与外部提供给其的时钟信号同步操作的半导体存储器件中，提供了第一部分，其在将给定命令输入到半导体存储器之后检测预定信号的状态; 以及第二部分，其基于预定信号的状态将半导体存储器件设置为在没有外部信号的情况下执行刷新操作的自刷新模式。
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公开(公告)号：US07184296B2
公开(公告)日：2007-02-27
申请号：US11069940
申请日：2005-03-03
申请人： Atsushi Hatakeyama , Toshimi Ikeda , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Atsushi Hatakeyama , Toshimi Ikeda , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C11/00
CPC分类号： G11C16/28
摘要： A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.
摘要翻译： 存储器件具有用于连接到存储单元的数据线（DATA-BUS），用于参考的参考线（Reference-BUS），预充电电路（101），负载电路（102）和放大器电路（103） ）。 预充电电路连接到数据线和参考线，并配置为对数据线和参考线进行预充电。 负载电路连接到数据线和参考线，并配置为向数据线施加第一恒定电流，并将比第一恒定电流小的第二恒定电流施加到参考线。 放大电路连接到数据线和参考线，并被配置为放大数据线与参考线之间的差分电压。
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