公开(公告)号：US07683492B2

公开(公告)日：2010-03-23

申请号：US11658638

申请日：2005-07-26

Applicant: Kenji Yoshida

Inventor： Kenji Yoshida

IPC: H01L25/18 ,  H01L25/04

CPC classification number: H01L23/5386 ,  H01L25/18 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/48

Abstract: The present invention provides a semiconductor device which can realize the mounting of a plurality of chips at a high-speed, with high packaging density and at a low cost. In mounting a memory device chip 103 and an ASIC 104 on a wiring chip 102, connection pads 110, 116 are respectively formed along one opposing sides of the memory device chip 103 and the ASIC 104 on the wiring chip 102, the arrangement positions of the respective connection pads 110, 116 define the shortest distance assumes the shortest distance therebetween and, at the same time wiring lines which are formed on the wiring chip 102 are also shortened. Accordingly, it is possible to mount the memory device chip 103 and the ASIC 104 on the wiring chip 102 with high packaging density and, at the same time, since the wiring distance can be shortened, the high speed operation can be realized.

Abstract translation: 本发明提供一种能够以高速，高封装密度和低成本实现多个芯片的安装的半导体装置。 在将存储器件芯片103和ASIC 104安装在布线芯片102上时，分别在布线芯片102上的存储器件芯片103和ASIC 104的相对侧分别形成连接焊盘110,116， 相应的连接焊盘110,116限定出最短的距离，并且同时缩短了布线芯片102上形成的布线。 因此，可以以高封装密度将存储器件芯片103和ASIC 104安装在布线芯片102上，同时由于可以缩短布线距离，可以实现高速运行。

公开(公告)号：US07664312B2

公开(公告)日：2010-02-16

申请号：US10583995

申请日：2004-12-24

Applicant: Kenji Yoshida

Inventor： Kenji Yoshida

IPC: H04N1/407 ,  G06K9/00

CPC classification number: G06F3/04886 ,  G06F3/0321 ,  G06K19/06037

Abstract: Making a dot pattern so that misalignment in a x direction and a y direction is alternately generated for every adjacent information dots on a virtual grid line, the misalignment is alternately generated in the x direction and the y direction for each dot and this results in that the alternate information dot is necessarily arranged on the same grid line. Therefore, in the case that an optical reading apparatus reads the dot pattern, a search algorithm of a virtual grid line is simplified on an image memory. As a result, the grid point on the image memory is also easy. Therefore, without using a complicated program, it is possible to speed up the reading speed of the dot pattern.

Abstract translation: 对于虚拟网格线上的每个相邻的信息点交替地产生点图案，使得在轴方向和ay方向上的未对准，对于每个点，在x方向和y方向上交替地产生未对准，并且这导致交替 信息点必须排列在相同的网格线上。 因此，在光学读取装置读取点阵图形的情况下，在图像存储器上简化虚拟网格线的搜索算法。 因此，图像存储器上的网格点也很容易。 因此，在不使用复杂程序的情况下，能够加快点图案的读取速度。

公开(公告)号：US20090262071A1

公开(公告)日：2009-10-22

申请号：US11991928

申请日：2006-09-13

Applicant: Kenji Yoshida

Inventor： Kenji Yoshida

IPC: G09G5/08 ,  G06K15/10

CPC classification number: G06F3/04815 ,  G01C21/3614 ,  G01C21/3623 ,  G01C21/3664 ,  G06F3/0321 ,  G06F3/03545 ,  G06F3/0485 ,  G06K19/06009 ,  G09B29/102

Abstract: To realize a user-friendly medium and information output thereof by defining a plurality of information in the same region of a dot pattern printed on a surface of a medium, such as a map or the like, and selectively outputting the information through an imaging operation of an imaging unit. [Means for Resolution] A dot pattern that is printed on a medium to be superimposed on a map or the like includes coordinate information and code information. Therefore, information corresponding to the coordinate information and information corresponding to the code information can be selectively and repetitively output.

Abstract translation: 通过在印刷在诸如地图等的介质的表面上的点图案的相同区域中定义多个信息来实现用户友好的介质及其信息输出，并且通过成像操作选择性地输出信息 的成像单元。 [解决方法]打印在要叠加在地图等上的介质上的点图案包括坐标信息和代码信息。 因此，可以选择性地和重复地输出与坐标信息相对应的信息和与代码信息相对应的信息。

公开(公告)号：US20090246654A1

公开(公告)日：2009-10-01

申请号：US12405710

申请日：2009-03-17

Applicant: Masafumi Asano ,  Kenji Yoshida ,  Masahiro Kanno

Inventor： Masafumi Asano ,  Kenji Yoshida ,  Masahiro Kanno

IPC: G03F7/20

CPC classification number: G03F7/70641 ,  G03F7/70625

Abstract: An evaluation method for lithography apparatus including a coating unit, an exposure unit, a heating unit and a development unit, the evaluation method including forming an evaluation resist pattern by using the lithography apparatus, the evaluation resist pattern including first and second evaluation patterns, the first and second evaluation patterns having different peripheral environments, measuring dimensions of the first and second evaluation patterns to obtain a dimensional difference between the first and second resist evaluation patterns, estimating an exposure dose of a resist when the resist is exposed by the exposure unit, the estimating the exposure dose being performed based on the dimensional difference between the first and second resist evaluation patterns, and estimating an effective heating temperature of the resist when the resist is heated by the heating unit, the estimating the effective heating temperature being performed based on the estimated exposure dose and the dimensional difference.

Abstract translation: 一种包括涂布单元，曝光单元，加热单元和显影单元的光刻设备的评估方法，所述评估方法包括通过使用光刻设备形成评估抗蚀剂图案，所述评估抗蚀剂图案包括第一和第二评估图案， 第一和第二评估图案具有不同的外围环境，测量第一和第二评估图案的尺寸以获得第一和第二抗蚀剂评估图案之间的尺寸差异，当抗蚀剂被曝光单元曝光时估计抗蚀剂的曝光剂量， 基于第一和第二抗蚀剂评估图案之间的尺寸差来估计正在进行的曝光剂量，以及当加热单元加热抗蚀剂时估计抗蚀剂的有效加热温度，基于 估计暴露剂量和t 他的尺寸差异。

公开(公告)号：US20090224241A1

公开(公告)日：2009-09-10

申请号：US11658638

申请日：2005-07-26

Applicant: Kenji Yoshida

Inventor： Kenji Yoshida

IPC: H01L23/52 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L25/18 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/48

Abstract: The present invention provides a semiconductor device which can realize the mounting of a plurality of chips at a high-speed, with high packaging density and at a low cost. In mounting a memory device chip 103 and an ASIC 104 on a wiring chip 102, connection pads 110, 116 are respectively formed along one opposing sides of the memory device chip 103 and the ASIC 104 on the wiring chip 102, the arrangement positions of the respective connection pads 110, 116 define the shortest distance assumes the shortest distance therebetween and, at the same time wiring lines which are formed on the wiring chip 102 are also shortened. Accordingly, it is possible to mount the memory device chip 103 and the ASIC 104 on the wiring chip 102 with high packaging density and, at the same time, since the wiring distance can be shortened, the high speed operation can be realized.

Abstract translation: 本发明提供一种能够以高速，高封装密度和低成本实现多个芯片的安装的半导体装置。 在将存储器件芯片103和ASIC 104安装在布线芯片102上时，分别在布线芯片102上的存储器件芯片103和ASIC 104的相对侧分别形成连接焊盘110,116， 相应的连接焊盘110,116限定出最短的距离，并且同时缩短了布线芯片102上形成的布线。 因此，可以以高封装密度将存储器件芯片103和ASIC 104安装在布线芯片102上，同时由于可以缩短布线距离，可以实现高速运行。

公开(公告)号：US20080133999A1

公开(公告)日：2008-06-05

申请号：US11978631

申请日：2007-10-30

Applicant: Yosuke Kondo ,  Kenji Yoshida

Inventor： Yosuke Kondo ,  Kenji Yoshida

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/1105 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/3723 ,  H03M13/3738 ,  H03M13/3746 ,  H03M13/451 ,  H03M13/458

Abstract: According one embodiment, after receiving, as a received bit sequence, an information bit sequence which has been encoded for an error correction in the form of connecting an error correcting code to the outside of an LDPC code, the received bit sequence is subjected to the LDPC decoding, and then subjected to an error correction corresponding to the error correcting code. When the error correction corresponding to the error correcting code is impossible, a bit with low reliability is detected from the received bit sequence subjected to the LDPC decoding, and the bit is inverted, and then the received bit sequence with the inverted bit is subjected to an error correction corresponding to the error correcting code.

Abstract translation: 根据一个实施例，在接收到的比特序列接收到以纠错码连接到LDPC码的外部的纠错编码的信息比特序列后，接收的比特序列经受 LDPC解码，然后进行与纠错码对应的纠错。 当与纠错码相对应的纠错是不可能的时，从经过LDPC解码的接收到的比特序列中检测出具有低可靠性的比特，并且该比特被反转，然后将接收到的具有反相比特的比特序列 对应于纠错码的纠错。

公开(公告)号：US20080128637A1

公开(公告)日：2008-06-05

申请号：US11607305

申请日：2006-12-01

Applicant: Kenji Yoshida ,  Takashi Mitsuhashi ,  Shohei Matsushita ,  Akira Fujimura

Inventor： Kenji Yoshida ,  Takashi Mitsuhashi ,  Shohei Matsushita ,  Akira Fujimura

IPC: G21K5/04

CPC classification number: H01J37/3174 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/20

Abstract: A method for particle beam lithography, such as electron beam (EB) lithography, includes predefining a stencil design having a plurality of cell patterns with information from a cell library, fabricating the stencil design, synthesizing a functional description into a logic circuit design after predefining the stencil design so that one or more characteristics of the stencil design are considered during synthesizing of the functional description into the logic circuit design, optimizing the logic circuit design, generating a layout design from the optimized logic circuit design, and forming the logic circuit on a substrate according to the stencil design and the layout design.

Abstract translation: 用于粒子束光刻的方法，例如电子束（EB）光刻，包括预定义具有多个单元图案的模板设计，其具有来自单元库的信息，制造模板设计，在预定义之后将功能描述合成为逻辑电路设计 模板设计使得在将逻辑电路设计中的功能描述合成期间考虑模板设计的一个或多个特性，优化逻辑电路设计，从优化的逻辑电路设计生成布局设计，并且形成逻辑电路 根据模板设计和布局设计的基材。

公开(公告)号：US20080043258A1

公开(公告)日：2008-02-21

申请号：US11794174

申请日：2004-12-28

Applicant: Kenji Yoshida

Inventor： Kenji Yoshida

IPC: G06F15/00

CPC classification number: G06K7/1417 ,  G06K19/06037

Abstract: A quadrangular or rectangular area on a medium surface of a printed material and the like is defined as a block. A straight line in a vertical direction and a horizontal direction nuclear along an edge of the block is defined as a reference grid line. A virtual grid point is placed at a predetermined interval on the reference grid line. A reference grid point dot is placed each on a virtual grid point on the horizontal reference grid lines. A straight line connecting the reference grid point dots and virtual grid points on a vertical line is defined as a grid line. An intersection point of grid lines is defined as a virtual grid point. A dot pattern is generated by arranging one or more information dots having a distance and a direction on the base of the virtual grid point. An optical reading means is used to scan the dot pattern into image information. Then, the dot pattern is converted into a numerical value, and the information corresponding to the numerical information is read from a storage means and output.

Abstract translation: 在印刷材料等的介质表面上的四边形或矩形区域被定义为块。 沿着块的边缘沿垂直方向和水平方向的核的直线被定义为参考网格线。 虚拟网格点以参考网格线上的预定间隔放置。 参考网格点点分别放置在水平参考网格线上的虚拟网格点上。 连接垂直线上的参考网格点和虚拟网格点的直线被定义为网格线。 将网格线的交点定义为虚拟网格点。 通过在虚拟网格点的基础上布置具有距离和方向的一个或多个信息点来生成点图案。 光学读取装置用于将点图案扫描成图像信息。 然后，将点图案转换为数值，并从存储装置读取与数字信息相对应的信息并输出。

公开(公告)号：US20080012433A1

公开(公告)日：2008-01-17

申请号：US11818699

申请日：2007-06-14

Applicant: Kazuyuki Yamaguchi ,  Tetsuya Koyama ,  Yusuke Niimi ,  Kenji Yoshida

Inventor： Kazuyuki Yamaguchi ,  Tetsuya Koyama ,  Yusuke Niimi ,  Kenji Yoshida

IPC: H02K15/04

CPC classification number: H02K15/068 ,  Y10T29/49009 ,  Y10T29/49073 ,  Y10T29/53143 ,  Y10T29/53157

Abstract: Stator coils are inclined with respect to the axial direction of annularly arranged coil holding portions and such that at least parts of the stator coils overlap one another. In setting the stator coils on the coil holder, the stator coils are sequentially set on the coil holder in a predetermined direction, which is a coil setting direction, from the starting stator coil so as to overlap one another. The second section of the ending stator coil is set at the same position as a position where the first section of the starting stator coil is set in the circumferential direction or at a position advanced from the position where the first section of the starting stator coil is set in the circumferential direction. The ending stator coil is set on the coil holder to be further inward than the starting stator coil. Therefore, stator coils are evenly arranged.

Abstract translation: 定子线圈相对于环形布置的线圈保持部分的轴向倾斜，并且至少部分定子线圈彼此重叠。 在将定子线圈设置在线圈架上时，定子线圈从起动定子线圈沿预定方向（线圈设定方向）依次设置在线圈架上，以便彼此重叠。 终端定子线圈的第二部分设置在与起动定子线圈的第一部分在周向上或从起动定子线圈的第一部分的位置前进的位置处的位置相同的位置处 设置在圆周方向。 结束定子线圈设置在线圈架上比起动定子线圈更靠内侧。 因此，定子线圈均匀布置。

公开(公告)号：US20070202501A1

公开(公告)日：2007-08-30

申请号：US10574045

申请日：2004-09-29

Applicant: Kouji Matsushima ,  Shinichi Hashimoto ,  Masayuki Tsuchiya ,  Yuichi Hirata ,  Kenji Yoshida ,  Kazuyuki Ojima

Inventor： Kouji Matsushima ,  Shinichi Hashimoto ,  Masayuki Tsuchiya ,  Yuichi Hirata ,  Kenji Yoshida ,  Kazuyuki Ojima

IPC: C12Q1/68 ,  G01N33/53 ,  A61K38/17 ,  C07H21/04 ,  C12P21/06 ,  C07K14/705

CPC classification number: C07K14/705 ,  A61K31/00 ,  G01N33/564 ,  G01N33/566 ,  G01N2500/00

Abstract: Purified immunocytes were analyzed for expression frequencies, and the NKIR gene expressed specifically in natural killer (NK) cells was successfully identified. The NKIR gene encodes a receptor. Agonists and antagonists for the receptor can be identified by using the receptor.

Abstract translation: 分析纯化的免疫细胞的表达频率，并且成功鉴定了在自然杀伤（NK）细胞中特异表达的NKIR基因。 NKIR基因编码受体。 用于受体的激动剂和拮抗剂可以通过使用受体来鉴定。