-
公开(公告)号：US20090111281A1
公开(公告)日：2009-04-30
申请号：US12257953
申请日：2008-10-24
IPC分类号： H01L21/31
CPC分类号： H01L21/3146 , H01L21/0337 , H01L21/0338
摘要： A method for doubling the frequency of a lithographic process using a photo-resist template mask is described. A device layer having a photo-resist layer formed thereon is first provided. The photo-resist layer is patterned to form a photo-resist template mask. A spacer-forming material layer is deposited over the photo-resist template mask. The spacer-forming material layer is etched to form a spacer mask and to expose the photo-resist template mask. The photo-resist template mask is then removed and an image of the spacer mask is finally transferred to the device layer.
摘要翻译： 描述了使用光致抗蚀剂模板掩模使光刻工艺的频率加倍的方法。 首先提供其上形成有光致抗蚀剂层的器件层。 将光致抗蚀剂层图案化以形成光致抗蚀剂模板掩模。 在光致抗蚀剂模板掩模上沉积间隔物形成材料层。 蚀刻间隔物形成材料层以形成间隔物掩模并露出光刻胶模板掩模。 然后去除光刻胶模板掩模，并且最终将间隔掩模的图像转移到器件层。
-
公开(公告)号：US20080026584A1
公开(公告)日：2008-01-31
申请号：US11492316
申请日：2006-07-25
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/02123 , H01L21/02271 , H01L21/02337 , H01L21/31612
摘要： A gate hard mask is deposited on a gate structure using low pressure chemical vapor deposition (LPCVD). By doing so, the wet etch removal ratio (WERR) of the gate hard mask relative to the underlying polysilicon gate layer is increased when compared to prior art hard masks. The LPCVD gate hard mask will not only etch faster than prior art hard masks, but it will also reduce undercutting of the gate oxide. To provide additional control of the wet etch rate, the LPCVD hard mask can be annealed. The annealing can be tailored to achieve the desired etching rate.
摘要翻译： 使用低压化学气相沉积（LPCVD）将栅极硬掩模沉积在栅极结构上。 通过这样做，与现有技术的硬掩模相比，栅极硬掩模相对于下面的多晶硅栅极层的湿蚀刻去除率（WERR）增加。 LPCVD栅极硬掩模将不仅比现有技术的硬掩模蚀刻更快，而且还将减少栅极氧化物的底切。 为了提供对湿蚀刻速率的额外控制，LPCVD硬掩模可被退火。 可以定制退火以实现所需的蚀刻速率。
-
33.发明授权公开(公告)号：US06853043B2
公开(公告)日：2005-02-08
申请号：US10288123
申请日：2002-11-04
IPC分类号： C03C17/22 , C23C16/30 , H01L21/768 , H01L31/0232
CPC分类号： H01L21/76811 , C03C17/22 , C03C2217/213 , C03C2217/282 , C23C16/30 , H01L21/76801 , H01L21/76808 , H01L21/76813
摘要： A layer of antireflective coating (ARC) material for use in photolithographic processing. In one embodiment the ARC material has the formula SiwOxHy:Cz, where w, x, y and z represent the atomic percentage of silicon, oxygen, hydrogen and carbon, respectively, in the material and where w is between 35 and 55, x is between 35 and 55, y is between 4 and 15, z is between 0 and 3 and the atomic percentage of nitrogen in the material is less than or equal to 1 atomic percent.
摘要翻译： 用于光刻处理的一层抗反射涂层（ARC）材料。 在一个实施方案中，ARC材料具有式SiwO x H y：Cz，其中w，x，y和z分别表示材料中硅，氧，氢和碳的原子百分比，其中w在35和55之间，x是 在35和55之间，y在4和15之间，z在0和3之间，材料中氮的原子百分比小于或等于1原子％。
-
34.发明授权公开(公告)号：US08084310B2
公开(公告)日：2011-12-27
申请号：US12603371
申请日：2009-10-21
IPC分类号： H01L21/00
CPC分类号： H01L21/0337
摘要： Embodiments of the present invention pertain to methods of forming patterned features on a substrate having a reduced pitch in two dimensions as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask. A spacer layer is formed over a two-dimensional square grid of cores with a thickness chosen to leave a dimple at the center of four cores on the corners of a square. The spacer layer is etched back to reveal the substrate at the centers of the square. Removing the core material results in double the pattern density of the lithographically defined grid of cores. The regions of exposed substrate may be filled again with core material and the process repeated to quadruple the pattern density.
摘要翻译： 本发明的实施例涉及在使用单个高分辨率光掩模的标准光刻处理技术的可能性方面，在具有减小的间距的基板上形成图案化特征的方法。 间隔层形成在芯的二维正方形网格上，其厚度被选择为在正方形的角上的四个芯的中心处留下凹坑。 将间隔层回蚀刻以在正方形的中心露出基底。 去除核心材料会导致光刻图形格网格的图案密度增加一倍。 暴露的衬底的区域可以再次用芯材料填充，并且重复该过程以使图案密度增加四倍。
-
35.发明申请公开(公告)号：US20110223773A1
公开(公告)日：2011-09-15
申请号：US13111306
申请日：2011-05-19
IPC分类号： H01L21/302
CPC分类号： H01L21/02115 , C23C14/02 , C23C14/0605 , C23C14/35 , H01L21/02266 , H01L21/02354 , H01L21/2236 , H01L21/26513 , H01L21/268 , H01L21/3146
摘要： A plasma enhanced physical vapor deposition process deposits an amorphous carbon layer on an ion-implanted wafer for use in dynamic surface annealing of the wafer with an intense line beam of a laser wavelength. The deposition process is carried out at a wafer temperature below the dopant clustering threshold temperature, and includes introducing the wafer into a chamber having a carbon-containing target overlying the wafer, and furnishing a carrier gas into the chamber. The process further includes generating a wafer bias voltage and applying target source power to the carbon-containing target sufficient to produce ion bombardment of the carbon-containing target. The wafer bias voltage is set to a level at which the amorphous carbon layer that is deposited has a desired extinction coefficient at the laser wavelength.
摘要翻译： 等离子体增强的物理气相沉积工艺在离子注入晶片上沉积无定形碳层，用于具有激光波长的强线束的晶片的动态表面退火。 沉积工艺在低于掺杂剂聚集阈值温度的晶片温度下进行，并且包括将晶片引入到具有覆盖晶片的含碳靶的腔室中，并将载气提供到腔室中。 该方法还包括产生晶片偏置电压并将目标源功率施加到含碳靶足以产生含碳靶的离子轰击。 将晶片偏置电压设定为在激光波长处具有期望的消光系数的被沉积的无定形碳层的水平。
-
公开(公告)号：US07989366B2
公开(公告)日：2011-08-02
申请号：US11844810
申请日：2007-08-24
申请人： Jeffrey C. Munro , Srinivas D. Nemani , Young S. Lee , Marlon Menezes , Christopher Dennis Bencher , Vijay Parihar
发明人： Jeffrey C. Munro , Srinivas D. Nemani , Young S. Lee , Marlon Menezes , Christopher Dennis Bencher , Vijay Parihar
IPC分类号： H01L21/00
CPC分类号： H01L21/268 , H01L21/26513
摘要： Methods are disclosed for activating dopants in a doped semiconductor substrate. A carbon precursor is flowed into a substrate processing chamber within which the doped semiconductor substrate is disposed. A plasma is formed from the carbon precursor in the substrate processing chamber. A carbon film is deposited over the substrate with the plasma. A temperature of the substrate is maintained while depositing the carbon film less than 500° C. The deposited carbon film is exposed to electromagnetic radiation for a period less than 10 ms, and has an extinction coefficient greater than 0.3 at a wavelength comprised by the electromagnetic radiation.
摘要翻译： 公开了用于激活掺杂半导体衬底中的掺杂剂的方法。 碳前体流入其中设置掺杂半导体衬底的衬底处理室。 在基板处理室中由碳前体形成等离子体。 用等离子体沉积在衬底上的碳膜。 在沉积低于500℃的碳膜的同时保持基板的温度。沉积的碳膜暴露于电磁辐射小于10ms的时间段，并且在电磁波包括的波长处具有大于0.3的消光系数 辐射。
-
公开(公告)号：US07608300B2
公开(公告)日：2009-10-27
申请号：US10650941
申请日：2003-08-27
CPC分类号： C23C16/4401 , C23C16/0245 , C23C16/56
摘要： A variety of techniques may be employed alone or in combination to reduce the incidence of defects arising in dielectric stack structures formed by chemical vapor deposition (CVD). Incidence of a first defect type attributable to reaction between an unreacted species of a prior CVD step and reactants of a subsequent CVD step, is reduced by exposing a freshly-deposited dielectric layer to a plasma before any additional layers are deposited. Incidence of a second defect type attributable to the presence of incompletely vaporized CVD liquid precursor material, is reduced by exposing the freshly-deposited dielectric layer to a plasma, and/or by continuing the flow of carrier gas through an injection valve for a period beyond the conclusion of the CVD step.
摘要翻译： 各种技术可以单独使用或组合使用以减少通过化学气相沉积（CVD）形成的介电堆叠结构中产生的缺陷的发生率。 通过在沉积任何另外的层之前将新沉积的介电层暴露于等离子体，可以减少归因于现有CVD步骤的未反应物质与随后的CVD步骤的反应物之间的反应的第一缺陷类型的发生。 归因于存在不完全蒸发的CVD液体前体材料的第二种缺陷类型的发生通过将新沉积的介电层暴露于等离子体和/或通过使载气通过喷射阀的流动持续一段时间来减少 CVD步骤的结论。
-
38.发明授权Dynamic surface annealing of implanted dopants with low temperature HDPCVD process for depositing a high extinction coefficient optical absorber layer 失效用低温HDPCVD工艺的注入掺杂剂的动态表面退火，用于沉积高消光系数光吸收层公开(公告)号：US07588990B2
公开(公告)日：2009-09-15
申请号：US11692778
申请日：2007-03-28
IPC分类号： H01L21/336
CPC分类号： C23C16/26 , C23C14/5813 , C23C16/56 , H01L21/26513 , H01L21/268
摘要： A plasma enhanced physical vapor deposition process deposits an amorphous carbon layer on an ion-implanted wafer for use in dynamic surface annealing of the wafer with an intense line beam of a laser wavelength. The deposition process is carried out at a wafer temperature below the dopant clustering threshold temperature, and includes introducing the wafer into a chamber and furnishing a hydrocarbon process gas into the chamber, preferably propylene (C3H6) or toluene (C7H8) or acetylene (C2H2) or a mixture of acetylene and methane (C2H4). The process further includes inductively coupling RF plasma source power into the chamber while and applying RF plasma bias power to the wafer. The wafer bias voltage is set to a level at which the amorphous carbon layer that is deposited has a desired stress (compressive or tensile). We have discovered that at a wafer temperature less than or equal to 475 degrees C., total RF plasma source power of 4000 Watts at about 2 MHz, RF plasma bias power of 2000-3000 Watts at about 13.56 MHz and a chamber pressure in a range of 3 mTorr to 2 Torr, the deposited amorphous carbon layer has a surprising combination of high absorption and high strength and excellent step coverage.
摘要翻译： 等离子体增强的物理气相沉积工艺在离子注入晶片上沉积无定形碳层，用于具有激光波长的强线束的晶片的动态表面退火。 沉积工艺在低于掺杂剂聚集阈值温度的晶片温度下进行，并且包括将晶片引入室中并将烃工艺气体提供到室中，优选丙烯（C 3 H 6）或甲苯（C 7 H 8）或乙炔（C 2 H 2） 或乙炔和甲烷（C2H4）的混合物。 该方法还包括将RF等离子体源功率感应耦合到腔室中，同时将RF等离子体偏置功率施加到晶片。 将晶片偏置电压设定为沉积的无定形碳层具有期望的应力（压缩或拉伸）的水平。 我们已经发现，在晶片温度小于或等于475摄氏度的情况下，在大约2MHz处的4000瓦特的RF射频等离子体源功率，在约13.56MHz的RF等离子体等离子体功率为2000-3000瓦， 3mTorr至2Torr的范围，沉积的非晶碳层具有高吸收和高强度以及优异的台阶覆盖的令人惊奇的组合。
-
39.发明申请公开(公告)号：US20080257864A1
公开(公告)日：2008-10-23
申请号：US12082494
申请日：2008-04-10
CPC分类号： C23C16/4401 , C23C16/0245 , C23C16/56
摘要： A variety of techniques may be employed alone or in combination to reduce the incidence of defects arising in dielectric stack structures formed by chemical vapor deposition (CVD). Incidence of a first defect type attributable to reaction between an unreacted species of a prior CVD step and reactants of a subsequent CVD step, is reduced by exposing a freshly-deposited dielectric layer to a plasma before any additional layers are deposited. Incidence of a second defect type attributable to the presence of incompletely vaporized CVD liquid precursor material, is reduced by exposing the freshly-deposited dielectric layer to a plasma, and/or by continuing the flow of carrier gas through an injection valve for a period beyond the conclusion of the CVD step.
摘要翻译： 各种技术可以单独使用或组合使用以减少通过化学气相沉积（CVD）形成的介电堆叠结构中产生的缺陷的发生率。 通过在沉积任何另外的层之前将新沉积的介电层暴露于等离子体，可以减少归因于现有CVD步骤的未反应物质与随后的CVD步骤的反应物之间的反应的第一缺陷类型的发生。 归因于存在不完全蒸发的CVD液体前体材料的第二种缺陷类型的发生通过将新沉积的介电层暴露于等离子体和/或通过使载气通过喷射阀的流动持续一段时间来减少 CVD步骤的结论。
-
公开(公告)号：US07365014B2
公开(公告)日：2008-04-29
申请号：US10768919
申请日：2004-01-30
申请人： Christopher Dennis Bencher , Melvin Warren Montgomery , Alexander Buxbaum , Yung-Hee Yvette Lee , Jian Ding , Gilad Almogy , Wendy H. Yeh
发明人： Christopher Dennis Bencher , Melvin Warren Montgomery , Alexander Buxbaum , Yung-Hee Yvette Lee , Jian Ding , Gilad Almogy , Wendy H. Yeh
IPC分类号： H01L21/66 , H01L21/311 , H01L21/302 , H01L21/44 , H01L21/461
摘要： We have reduced the critical dimension bias for reticle fabrication. Pattern transfer to the radiation-blocking layer of the reticle substrate essentially depends upon use of a hard mask to which the pattern is transferred from a photoresist. The photoresist pull back which occurs during pattern transfer to the hard mask is minimalized. In addition, a hard mask material having anti-reflective properties which are matched to the reflective characteristics of the radiation-blocking layer enables a reduction in critical dimension size and an improvement in the pattern feature integrity in the hard mask itself. An anti-reflective hard mask layer left on the radiation-blocking layer provides functionality when the reticle is used in a semiconductor device manufacturing process.
摘要翻译： 我们已经减少了标线制造的临界尺寸偏差。 图案转印到掩模版基板的辐射阻挡层基本上取决于使用从光致抗蚀剂转移图案的硬掩模。 在图案转印到硬掩模期间发生的光致抗蚀剂拉回最小化。 此外，具有与防辐射层的反射特性相匹配的抗反射性能的硬掩模材料能够降低临界尺寸尺寸，并改善硬掩模本身的图案特征完整性。 当在半导体器件制造工艺中使用掩模版时，留在辐射阻挡层上的抗反射硬掩模层提供功能。
-
-
-
-
-
-
-
-
-
搜索结果
41 条记录 (耗时 0.039 秒)
