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47 条记录 (耗时 0.039 秒)

    Phase change memory devices having dual lower electrodes
    31.
    发明授权
    Phase change memory devices having dual lower electrodes 有权
    具有双下电极的相变存储器件

    公开(公告)号：US07696508B2

    公开(公告)日：2010-04-13

    申请号：US11932781

    申请日：2007-10-31

    申请人： Yoon-Jong Song ,  Kyung-Chang Ryoo ,  Dong-Won Lim

    发明人： Yoon-Jong Song ,  Kyung-Chang Ryoo ,  Dong-Won Lim

    IPC分类号： H01L29/43

    CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/1675

    摘要： A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.

    摘要翻译： 半导体器件包括半导体衬底和设置在衬底上的下层间绝缘层。 包括通过下层间绝缘层并露出衬底的开口。 掩埋绝缘图案设置在开口中。 依次堆叠第一和第二导电层图案以围绕埋入绝缘图案的侧壁和底部。 包括相变材料图案，其设置在与第二导电层图案的顶表面接触并且与第一导电层图案间隔开的下层间绝缘层上。 包括覆盖下层间绝缘层的上层间绝缘层和相变材料图案。 包括导电塞，其穿过上层间绝缘层并电连接到相变材料图案。 还提供了制造半导体器件的方法。

    Phase-Changeable Memory Devices Having Reduced Susceptibility to Thermal Interference
    32.
    发明申请
    Phase-Changeable Memory Devices Having Reduced Susceptibility to Thermal Interference 有权
    相位可变的存储器件降低了对热干扰的敏感性

    公开(公告)号：US20090127538A1

    公开(公告)日：2009-05-21

    申请号：US12265262

    申请日：2008-11-05

    申请人： Kyung-Chang Ryoo ,  Jong-Woo Ko ,  Yoon-Jong Song

    发明人： Kyung-Chang Ryoo ,  Jong-Woo Ko ,  Yoon-Jong Song

    IPC分类号： H01L47/00

    CPC分类号： H01L45/143 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675 ,  Y10S257/903

    摘要： A non-volatile memory array includes an array of phase-changeable memory elements that are electrically insulated from each other by at least a first electrically insulating region extending between the array of phase-changeable memory elements. The first electrically insulating region includes a plurality of voids therein. Each of these voids extends between a corresponding pair of phase-changeable memory cells in the non-volatile memory array and, collectively, the voids form an array of voids in the first electrically insulating region.

    摘要翻译： 非易失性存储器阵列包括相变存储元件的阵列，它们通过在可相变存储元件阵列之间延伸的至少第一电绝缘区域彼此电绝缘。 第一电绝缘区域中包括多个空隙。 这些空隙中的每一个在非易失性存储器阵列中相应的一对相位可变存储单元之间延伸，并且总体上空隙在第一电绝缘区域中形成一组空隙。

    Semiconductor device having ferroelectric material capacitor and method of making the same
    33.
    发明申请
    Semiconductor device having ferroelectric material capacitor and method of making the same 失效

    公开(公告)号：US20060003473A1

    公开(公告)日：2006-01-05

    申请号：US11218972

    申请日：2005-09-02

    申请人： Yoon-Jong Song

    发明人： Yoon-Jong Song

    IPC分类号： H01L21/00

    CPC分类号： H01L27/11502 ,  H01L21/28568 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

    摘要： The present invention relates to the field of a semiconductor device having a ferroelectric material capacitor and method of making the same. The semiconductor device includes a capacitor having a triple-level oxygen barrier layer pattern formed by an oxygen barrier metal layer, a material layer formed of a conductive solid solution by compounding the oxygen barrier metal layer and oxygen, and an oxygen barrier metal on an interlayer dielectric with a contact plug. The capacitor also has an electrode and a ferroelectric film electrically contacting to the oxygen barrier layer. Further, a wetting layer is formed between the oxygen barrier layer and the contact plug, and an iridium oxygen layer is formed between the oxygen barrier layer and a capacitor electrode.

    Ferroelectric memory device and method of forming the same
    34.
    发明授权
    Ferroelectric memory device and method of forming the same 失效

    公开(公告)号：US06737694B2

    公开(公告)日：2004-05-18

    申请号：US10066172

    申请日：2002-01-30

    申请人： Ki-Nam Kim ,  Yoon-Jong Song

    发明人： Ki-Nam Kim ,  Yoon-Jong Song

    IPC分类号： H01L27108

    CPC分类号： H01L27/11502 ,  H01L21/3144 ,  H01L21/3185 ,  H01L21/76895 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60

    摘要： A ferroelectric memory device along with a method of forming the same are provided. A first interlayer insulating layer is formed on a semiconductor substrate. A buried contact structure is formed on the first interlayer insulating layer. The buried contact structure is electrically connected to the substrate through a first contact hole extending through the first interlayer insulating layer. A blocking layer covers or encapsulates the buried contact structure and the first interlayer insulating layer. A second interlayer insulating layer is formed on the blocking layer. A ferroelectric capacitor formed on the second interlayer insulating layer and is electrically connected to the buried contact structure through a second contact hole that penetrates the second interlayer insulating layer and the blocking layer.

    Semiconductor device including uniform contact plugs and a method of manufacturing the same
    35.
    发明授权
    Semiconductor device including uniform contact plugs and a method of manufacturing the same 有权
    包括均匀接触塞的半导体器件及其制造方法

    公开(公告)号：US08203135B2

    公开(公告)日：2012-06-19

    申请号：US12697620

    申请日：2010-02-01

    申请人： Kyu-Rie Sim ,  Jung-Hoon Park ,  Yoon-Jong Song ,  Jae-Min Shin ,  Shin-Hee Han

    发明人： Kyu-Rie Sim ,  Jung-Hoon Park ,  Yoon-Jong Song ,  Jae-Min Shin ,  Shin-Hee Han

    IPC分类号： H01L29/41

    CPC分类号： H01L27/24 ,  H01L27/222

    摘要： A semiconductor device, a semiconductor module, an electronic apparatus and methods of fabricating and manufacturing the same are provided. The semiconductor device includes a lower interconnection formed on a substrate, a plurality of control patterns formed on the lower interconnection, a plurality of lower contact plug patterns formed on the control patterns, a plurality of storage patterns formed on the lower contact plug patterns, a plurality of upper electrodes formed on the storage patterns, and a plurality of upper interconnections formed on the upper electrodes. The lower contact plug patterns each include at least two contact holes having different sizes, a plurality of sidewall patterns formed on inner sidewalls of the two contact holes and wherein the sidewall patterns have different thicknesses from one another. The semiconductor device further includes a plurality of electrode patterns conformably formed on the inside of the sidewall patterns and having size errors less than 10%, and a plurality of filling patterns formed inside the electrode patterns and completely filling the inside of the contact holes.

    摘要翻译： 提供半导体器件，半导体模块，电子设备及其制造和制造方法。 半导体器件包括形成在衬底上的下互连，形成在下互连上的多个控制图案，形成在控制图案上的多个下接触插塞图案，形成在下接触插塞图案上的多个存储图案， 形成在存储图案上的多个上电极和形成在上电极上的多个上互连。 下接触插头图案各自包括具有不同尺寸的至少两个接触孔，多个侧壁图案形成在两个接触孔的内侧壁上，并且其中侧壁图案具有彼此不同的厚度。 半导体器件还包括多个沿着侧壁图案的内侧形成并且具有小于10％的尺寸误差的电极图案，以及形成在电极图案内并且完全填充接触孔内部的多个填充图案。

    Phase change memory devices having dual lower electrodes and methods of fabricating the same
    36.
    发明授权
    Phase change memory devices having dual lower electrodes and methods of fabricating the same 有权
    具有双下电极的相变存储器件及其制造方法

    公开(公告)号：US08129214B2

    公开(公告)日：2012-03-06

    申请号：US12709536

    申请日：2010-02-22

    申请人： Yoon-Jong Song ,  Kyung-Chang Ryoo ,  Dong-Won Lim

    发明人： Yoon-Jong Song ,  Kyung-Chang Ryoo ,  Dong-Won Lim

    IPC分类号： H01L21/00 ,  H01L45/00

    CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/1675

    摘要： A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.

    摘要翻译： 半导体器件包括半导体衬底和设置在衬底上的下层间绝缘层。 包括通过下层间绝缘层并露出衬底的开口。 掩埋绝缘图案设置在开口中。 依次堆叠第一和第二导电层图案以围绕埋入绝缘图案的侧壁和底部。 包括相变材料图案，其设置在与第二导电层图案的顶表面接触并且与第一导电层图案间隔开的下层间绝缘层上。 包括覆盖下层间绝缘层的上层间绝缘层和相变材料图案。 包括导电塞，其穿过上层间绝缘层并电连接到相变材料图案。 还提供了制造半导体器件的方法。

    Phase change memory device and method of fabricating the same
    39.
    发明申请
    Phase change memory device and method of fabricating the same 有权
    相变存储器件及其制造方法

    公开(公告)号：US20090242866A1

    公开(公告)日：2009-10-01

    申请号：US12382781

    申请日：2009-03-24

    申请人： Seung-Pil Ko ,  Jae-Hee Oh ,  Jung-Hoon Park ,  Yoon-Jong Song ,  Jae-Hyun Park ,  Dong-Won Lim

    发明人： Seung-Pil Ko ,  Jae-Hee Oh ,  Jung-Hoon Park ,  Yoon-Jong Song ,  Jae-Hyun Park ,  Dong-Won Lim

    IPC分类号： H01L47/00 ,  H01L21/00

    CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1683

    摘要： A semiconductor device includes an insulating layer on a substrate, a first electrode in the insulating layer having a first upper surface and a second upper surface, a second electrode in the insulating layer spaced apart from the first electrode by a first distance and having a third upper surface and a fourth upper surface, the third upper surface being disposed at a substantially same level as the first upper surface, and the fourth upper surface being disposed at a substantially same level as the second upper surface, a first phase change material pattern covering a part of the first upper surface of the first electrode, and a second phase change material pattern covering a part of the third upper surface of the second electrode, wherein an interface region between the second phase change pattern and the second electrode is spaced apart from an interface region between the first phase change pattern and the first electrode by a second distance greater than the first distance.

    摘要翻译： 半导体器件在衬底上包括绝缘层，绝缘层中的第一电极具有第一上表面和第二上表面，绝缘层中的第二电极与第一电极隔开第一距离，并具有第三距离 上表面和第四上表面，所述第三上表面设置在与所述第一上表面基本相同的高度，所述第四上表面设置在与所述第二上表面基本相同的水平面上，所述第一相变材料图案覆盖 第一电极的第一上表面的一部分和覆盖第二电极的第三上表面的一部分的第二相变材料图案，其中第二相变图案和第二电极之间的界面区域与 所述第一相变图案和所述第一电极之间的界面区域大于所述第一距离的第二距离。

    Phase change memory and method of fabricating the same
    40.
    发明申请
    Phase change memory and method of fabricating the same 失效
    相变记忆及其制造方法

    公开(公告)号：US20090163023A1

    公开(公告)日：2009-06-25

    申请号：US12314884

    申请日：2008-12-18

    申请人： Yoon-Jong Song ,  Byung-Seo Kim ,  Kyung-Chang Ryoo

    发明人： Yoon-Jong Song ,  Byung-Seo Kim ,  Kyung-Chang Ryoo

    IPC分类号： H01L21/44

    CPC分类号： H01L45/1675 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144

    摘要： A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.

    摘要翻译： 制造相变存储器的方法包括在半导体衬底上形成下电极，在下电极上依次形成相变图案，上电极和硬掩模图案，硬掩模图案的底面宽度 大于硬掩模图案的顶表面的宽度，硬掩模图案的底表面面向上电极并且与硬掩模图案的顶表面相对，并且形成覆盖层以覆盖硬掩模图案的顶表面 硬掩模图案和硬掩模图案的侧壁，相变图案和上电极。