公开(公告)号：US08203135B2

公开(公告)日：2012-06-19

申请号：US12697620

申请日：2010-02-01

申请人： Kyu-Rie Sim ,  Jung-Hoon Park ,  Yoon-Jong Song ,  Jae-Min Shin ,  Shin-Hee Han

发明人： Kyu-Rie Sim ,  Jung-Hoon Park ,  Yoon-Jong Song ,  Jae-Min Shin ,  Shin-Hee Han

IPC分类号： H01L29/41

CPC分类号： H01L27/24 ,  H01L27/222

摘要： A semiconductor device, a semiconductor module, an electronic apparatus and methods of fabricating and manufacturing the same are provided. The semiconductor device includes a lower interconnection formed on a substrate, a plurality of control patterns formed on the lower interconnection, a plurality of lower contact plug patterns formed on the control patterns, a plurality of storage patterns formed on the lower contact plug patterns, a plurality of upper electrodes formed on the storage patterns, and a plurality of upper interconnections formed on the upper electrodes. The lower contact plug patterns each include at least two contact holes having different sizes, a plurality of sidewall patterns formed on inner sidewalls of the two contact holes and wherein the sidewall patterns have different thicknesses from one another. The semiconductor device further includes a plurality of electrode patterns conformably formed on the inside of the sidewall patterns and having size errors less than 10%, and a plurality of filling patterns formed inside the electrode patterns and completely filling the inside of the contact holes.

摘要翻译： 提供半导体器件，半导体模块，电子设备及其制造和制造方法。 半导体器件包括形成在衬底上的下互连，形成在下互连上的多个控制图案，形成在控制图案上的多个下接触插塞图案，形成在下接触插塞图案上的多个存储图案， 形成在存储图案上的多个上电极和形成在上电极上的多个上互连。 下接触插头图案各自包括具有不同尺寸的至少两个接触孔，多个侧壁图案形成在两个接触孔的内侧壁上，并且其中侧壁图案具有彼此不同的厚度。 半导体器件还包括多个沿着侧壁图案的内侧形成并且具有小于10％的尺寸误差的电极图案，以及形成在电极图案内并且完全填充接触孔内部的多个填充图案。

公开(公告)号：US07906773B2

公开(公告)日：2011-03-15

申请号：US12382781

申请日：2009-03-24

申请人： Seung-Pil Ko ,  Jae-Hee Oh ,  Jung-Hoon Park ,  Yoon-Jong Song ,  Jae-Hyun Park ,  Dong-Won Lim

发明人： Seung-Pil Ko ,  Jae-Hee Oh ,  Jung-Hoon Park ,  Yoon-Jong Song ,  Jae-Hyun Park ,  Dong-Won Lim

IPC分类号： H01L21/00

CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1683

摘要： A semiconductor device includes an insulating layer on a substrate, a first electrode in the insulating layer having a first upper surface and a second upper surface, a second electrode in the insulating layer spaced apart from the first electrode by a first distance and having a third upper surface and a fourth upper surface, the third upper surface being disposed at a substantially same level as the first upper surface, and the fourth upper surface being disposed at a substantially same level as the second upper surface, a first phase change material pattern covering a part of the first upper surface of the first electrode, and a second phase change material pattern covering a part of the third upper surface of the second electrode, wherein an interface region between the second phase change pattern and the second electrode is spaced apart from an interface region between the first phase change pattern and the first electrode by a second distance greater than the first distance.

摘要翻译： 半导体器件在衬底上包括绝缘层，绝缘层中的第一电极具有第一上表面和第二上表面，绝缘层中的第二电极与第一电极隔开第一距离，并具有第三距离 上表面和第四上表面，所述第三上表面设置在与所述第一上表面基本相同的高度，所述第四上表面设置在与所述第二上表面基本相同的水平面上，所述第一相变材料图案覆盖 第一电极的第一上表面的一部分和覆盖第二电极的第三上表面的一部分的第二相变材料图案，其中第二相变图案和第二电极之间的界面区域与 所述第一相变图案和所述第一电极之间的界面区域大于所述第一距离的第二距离。

公开(公告)号：US08043924B2

公开(公告)日：2011-10-25

申请号：US12420888

申请日：2009-04-09

申请人： Kyung-Chang Ryoo ,  Hong-Sik Jeong ,  Gi-Tae Jeong ,  Jung-Hoon Park ,  Yoon-Jong Song

发明人： Kyung-Chang Ryoo ,  Hong-Sik Jeong ,  Gi-Tae Jeong ,  Jung-Hoon Park ,  Yoon-Jong Song

IPC分类号： H01L21/82 ,  H01L21/36 ,  H01L21/4763 ,  H01L21/20

CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1675

摘要： In a method of forming a phase-change memory unit, a conductive layer is formed on a substrate having a trench. The conductive layer is planarized until the substrate is exposed to form a first electrode. A spacer partially covering the first electrode is formed. A phase-change material layer is formed on the first electrode and the second spacer. A second electrode is formed on the phase-change material layer. Reset/set currents of the phase-change memory unit may be reduced and deterioration of the phase-change material layer may be reduced and/or prevented.

摘要翻译： 在形成相变存储单元的方法中，在具有沟槽的衬底上形成导电层。 导电层被平坦化，直到基板暴露以形成第一电极。 形成部分地覆盖第一电极的间隔件。 相变材料层形成在第一电极和第二间隔物上。 在相变材料层上形成第二电极。 可以减少相变存储器单元的复位/设置电流，并且/或可以防止相变材料层的劣化。

公开(公告)号：US20090242866A1

公开(公告)日：2009-10-01

申请号：US12382781

申请日：2009-03-24

申请人： Seung-Pil Ko ,  Jae-Hee Oh ,  Jung-Hoon Park ,  Yoon-Jong Song ,  Jae-Hyun Park ,  Dong-Won Lim

发明人： Seung-Pil Ko ,  Jae-Hee Oh ,  Jung-Hoon Park ,  Yoon-Jong Song ,  Jae-Hyun Park ,  Dong-Won Lim

IPC分类号： H01L47/00 ,  H01L21/00

CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1683

摘要： A semiconductor device includes an insulating layer on a substrate, a first electrode in the insulating layer having a first upper surface and a second upper surface, a second electrode in the insulating layer spaced apart from the first electrode by a first distance and having a third upper surface and a fourth upper surface, the third upper surface being disposed at a substantially same level as the first upper surface, and the fourth upper surface being disposed at a substantially same level as the second upper surface, a first phase change material pattern covering a part of the first upper surface of the first electrode, and a second phase change material pattern covering a part of the third upper surface of the second electrode, wherein an interface region between the second phase change pattern and the second electrode is spaced apart from an interface region between the first phase change pattern and the first electrode by a second distance greater than the first distance.

摘要翻译： 半导体器件在衬底上包括绝缘层，绝缘层中的第一电极具有第一上表面和第二上表面，绝缘层中的第二电极与第一电极隔开第一距离，并具有第三距离 上表面和第四上表面，所述第三上表面设置在与所述第一上表面基本相同的高度，所述第四上表面设置在与所述第二上表面基本相同的水平面上，所述第一相变材料图案覆盖 第一电极的第一上表面的一部分和覆盖第二电极的第三上表面的一部分的第二相变材料图案，其中第二相变图案和第二电极之间的界面区域与 所述第一相变图案和所述第一电极之间的界面区域大于所述第一距离的第二距离。

公开(公告)号：US07978201B2

公开(公告)日：2011-07-12

申请号：US11519598

申请日：2006-09-12

申请人： Sung-Dae Cho ,  Seok-Jin Won ,  Jung-Hoon Park ,  Young-Min Jeong ,  Jae-Won Moon ,  Yun-Je Oh ,  Young-Ho Ha ,  Jong-Man Kim ,  Cheol-Hee Lee ,  Chang-Hwan Son

发明人： Sung-Dae Cho ,  Seok-Jin Won ,  Jung-Hoon Park ,  Young-Min Jeong ,  Jae-Won Moon ,  Yun-Je Oh ,  Young-Ho Ha ,  Jong-Man Kim ,  Cheol-Hee Lee ,  Chang-Hwan Son

IPC分类号： G09G5/02 ,  G09G5/10 ,  G09G5/00 ,  H04N5/57 ,  H04N1/46 ,  G06K9/40 ,  G02B27/00 ,  G09G3/30 ,  H04N7/18 ,  G06K9/20 ,  G02B1/10

CPC分类号： H04N1/6086 ,  G09G3/2003 ,  G09G5/02 ,  G09G2320/04 ,  G09G2320/0666 ,  G09G2340/06 ,  G09G2360/144 ,  H04N5/58 ,  H04N9/68 ,  H04N21/41407 ,  H04N21/42202 ,  H04N21/4318

摘要： A method for compensating an image produced by image means for implementing image information takes account of ambient illumination. Luminance of external background illumination around the image means is measured. The measured luminance of the background illumination is compared with preset tristimulus values and a reflectance factor of the image means, a comparison result is computed, and a control signal is generated to compensate luminance and chroma of an image. Luminance and chroma of the image means are compensated in response to the control signal.

摘要翻译： 用于补偿由用于实现图像信息的图像装置产生的图像的方法考虑了环境照明。 测量图像周围的外部背景照明的亮度。 将背景照明的测量亮度与预设的三刺激值和图像装置的反射率进行比较，计算比较结果，并生成控制信号以补偿图像的亮度和色度。 响应于控制信号补偿图像装置的亮度和色度。

公开(公告)号：US07889595B2

公开(公告)日：2011-02-15

申请号：US12346134

申请日：2008-12-30

申请人： Jung-Hoon Park

发明人： Jung-Hoon Park

IPC分类号： G11C8/00

CPC分类号： G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C2207/2254 ,  H03L7/00

摘要： A semiconductor memory device includes a clock inputting unit configured to receive a system clock and a data clock, a clock dividing unit configured to divide a frequency of the data clock to generate a data division clock and determining a phase of the data division clock according to a division control signal, a phase dividing unit configured to generate a plurality of multiple-phase data division clocks each having a predetermined phase difference according to the data division clock, and a first phase detecting unit configured to detect a phase of the system clock based on a predetermined selection clock among the multiple-phase data division clocks, and generate the division control signal according to the detection result.

摘要翻译： 一种半导体存储器件，包括：时钟输入单元，被配置为接收系统时钟和数据时钟;时钟分频单元，被配置为分频数据时钟的频率以产生数据分频时钟，并根据 分割控制信号，相位分割单元，被配置为根据数据分时钟产生各自具有预定相位差的多个多相数据分时钟;第一相位检测单元，被配置为基于系统时钟的相位检测 在多相数据分时钟之间的预定选择时钟上，并根据检测结果产生除法控制信号。

公开(公告)号：US07800397B2

公开(公告)日：2010-09-21

申请号：US11878924

申请日：2007-07-27

申请人： Jung-Hoon Park

发明人： Jung-Hoon Park

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： G11C7/1051 ,  G11C5/063 ,  G11C7/1057 ,  H03K19/0005

摘要： An on-die termination circuit of a semiconductor memory apparatus includes a comparator that compares a voltage corresponding to a normal code with a reference voltage to output a comparison signal. A code adjusting unit varies the normal code according to the comparison signal, outputs the varied normal code, and resets the normal code to a predetermined reset code or a variable fuse code.

摘要翻译： 半导体存储装置的片上终端电路包括比较器，其将与正常码相对应的电压与参考电压进行比较，以输出比较信号。 代码调整单元根据比较信号改变普通代码，输出变化的普通代码，并将普通代码复位到预定的复位代码或可变的熔丝代码。

公开(公告)号：US07502263B2

公开(公告)日：2009-03-10

申请号：US11606285

申请日：2006-11-30

申请人： Jung-Hoon Park

发明人： Jung-Hoon Park

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C8/08 ,  G11C16/12

摘要： A non-volatile semiconductor memory device and method of programming the non-volatile semiconductor memory device are disclosed. The non-volatile semiconductor memory device includes a selected word-line and unselected word-lines including at least one unselected word-line to which a first voltage signal is applied. The selected word-line is coupled to a selected memory transistor and receives a program voltage signal in response to a program voltage enable signal. A first voltage signal is applied to the at least one unselected word-line. The first voltage signal has a voltage level of a reduced pass voltage signal before the program voltage enable signal is activated and has a voltage level of a pass voltage signal while the program voltage enable signal is activated.

摘要翻译： 公开了非易失性半导体存储器件和非易失性半导体存储器件的编程方法。 非易失性半导体存储器件包括选择的字线和包括施加了第一电压信号的至少一个未选择字线的未选择字线。 所选择的字线被耦合到选定的存储晶体管，并且响应于编程电压使能信号而接收编程电压信号。 第一电压信号被施加到至少一个未选择的字线。 第一电压信号在编程电压使能信号被激活之前具有降低的通过电压信号的电压电平，并且在编程电压使能信号被激活时具有通过电压信号的电压电平。

公开(公告)号：US20080087926A1

公开(公告)日：2008-04-17

申请号：US11853039

申请日：2007-09-11

申请人： Jung-Hoon Park ,  Heung-Jin Joo

发明人： Jung-Hoon Park ,  Heung-Jin Joo

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/11507 ,  H01L27/11502 ,  H01L28/57

摘要： A method of forming a ferroelectric random access memory includes sequentially forming a conductive pattern, an etch-stop layer, a ferroelectric capacitor and an interlayer dielectric on a semiconductor substrate, which includes a first region and a second region. The ferroelectric capacitor is formed on the first region and the conductive pattern is formed on the second region. The interlayer dielectric is patterned to simultaneously form a first opening to expose a top surface of the ferroelectric capacitor and a second opening to expose a top surface of the etch-stop layer. The patterned interlayer dielectric is annealed in an ambient atmosphere, including oxygen atoms. The etch-stop layer exposed through the second opening is etched to expose a top surface of the conductive pattern. First and second top plugs are formed to connect to the ferroelectric capacitor and the conductive pattern through the first and second openings, respectively.

摘要翻译： 形成铁电随机存取存储器的方法包括：在包括第一区域和第二区域的半导体衬底上依次形成导电图案，蚀刻停止层，铁电电容器和层间电介质。 铁电电容器形成在第一区域上，导电图案形成在第二区域上。 图案化层间电介质以同时形成第一开口以暴露铁电电容器的顶表面和第二开口以暴露蚀刻停止层的顶表面。 图案化的层间电介质在包括氧原子的环境气氛中退火。 通过第二开口暴露的蚀刻停止层被蚀刻以暴露导电图案的顶表面。 形成第一和第二顶部插头，以分别通过第一和第二开口连接到铁电电容器和导电图案。

公开(公告)号：US07294876B2

公开(公告)日：2007-11-13

申请号：US11325633

申请日：2006-01-03

申请人： Heung-Jin Joo ,  Bon-Jae Koo ,  Jung-Hoon Park

发明人： Heung-Jin Joo ,  Bon-Jae Koo ,  Jung-Hoon Park

IPC分类号： H01L29/76 ,  H01L21/8242

CPC分类号： H01L27/11507 ,  H01L21/76846 ,  H01L21/7687 ,  H01L27/11502 ,  H01L28/57 ,  H01L28/65

摘要： An embodiment of the FeRAM includes a ferroelectric capacitor including a bottom electrode, a ferroelectric layer, and a top electrode. Strontium ruthenium oxide is formed between the bottom electrode and the ferroelectric layer and between the ferroelectric layer and the top electrode. A diffusion barrier layer including strontium ruthenium oxide and iridium is formed between the top electrode and a direct cell contact plug coupled to a plate line interconnecting top electrodes of ferroelectric capacitors. Thus, diffusion of nitrogen or metallic materials produced in subsequent processes is suppressed to prevent degradation of the ferroelectric layer.

摘要翻译： FeRAM的一个实施例包括具有底部电极，铁电体层和顶部电极的铁电电容器。 在底电极和铁电层之间以及铁电层和顶电极之间形成氧化钌。 包括氧化钌和铱的扩散阻挡层形成在顶部电极和连接到互连铁电电容器的顶部电极的板线的直接电池接触插塞之间。 因此，抑制了在后续工艺中产生的氮或金属材料的扩散以防止铁电层的劣化。