公开(公告)号：US20230290407A1

公开(公告)日：2023-09-14

申请号：US18321338

申请日：2023-05-22

Applicant: KIOXIA CORPORATION

Inventor： Tomonori TAKAHASHI ,  Masanobu SHIRAKAWA ,  Osamu TORII ,  Marie TAKADA

IPC: G11C11/56 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C11/5671 ,  G11C16/26 ,  G11C16/08 ,  G11C16/0483

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

公开(公告)号：US20230223090A1

公开(公告)日：2023-07-13

申请号：US18174916

申请日：2023-02-27

Applicant: KIOXIA CORPORATION

Inventor： Masanobu SHIRAKAWA ,  Tsukasa TOKUTOMI ,  Marie TAKADA

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C11/5671 ,  G11C16/0483 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.

公开(公告)号：US20230117717A1

公开(公告)日：2023-04-20

申请号：US18082759

申请日：2022-12-16

Applicant: KIOXIA CORPORATION

Inventor： Marie TAKADA ,  Masanobu SHIRAKAWA ,  Tsukasa TOKUTOMI

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/16 ,  G11C16/08 ,  G06F11/10 ,  G11C29/52 ,  G11C16/04

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.

公开(公告)号：US20230065159A1

公开(公告)日：2023-03-02

申请号：US17984309

申请日：2022-11-10

Applicant: Kioxia Corporation

Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Marie TAKADA ,  Masamichi FUJIWARA ,  Kazumasa YAMAMOTO ,  Naoaki KOKUBUN ,  Tatsuro HITOMI ,  Hironori UCHIKAWA

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11 ,  H03M13/37 ,  H03M13/29 ,  H03M13/15

Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.

公开(公告)号：US20220301653A1

公开(公告)日：2022-09-22

申请号：US17471539

申请日：2021-09-10

Applicant: Kioxia Corporation

Inventor： Marie TAKADA ,  Masanobu SHIRAKAWA

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C29/12 ,  G11C29/50

Abstract: According to one embodiment, a memory system includes: a controller configured to execute an error correction process on first data read from a first area at a first address of a memory device and determine a read level used for reading data at the first address according to a result of the correction process. The controller executes the correction process on first frame data of the first data. When the correction process on the first frame data has failed, the controller executes the correction process on second frame data of the first data. When the correction process on the second frame data has succeeded, the controller determines the read level based on a result of comparison between the second frame data and a result of the correction process on the second frame data.

公开(公告)号：US20220059164A1

公开(公告)日：2022-02-24

申请号：US17188046

申请日：2021-03-01

Applicant: Kioxia Corporation

Inventor： Marie TAKADA ,  Masanobu SHIRAKAWA

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G06F3/06

Abstract: A memory device according to one embodiment includes a memory cell array, bit lines, amplifier units, a controller, and a register. The memory cell array includes a memory cell that stores data nonvolatilely. The bit lines are connected to the memory cell array. The sense amplifier units are connected to the bit lines, respectively. The controller performs a write operation. The register stores status information of the write operation. The memory cell array includes a first storage region specified by a first address. The plurality of sense amplifier modules include a buffer region capable of storing data.

公开(公告)号：US20210089233A1

公开(公告)日：2021-03-25

申请号：US16816439

申请日：2020-03-12

Applicant: Kioxia Corporation

Inventor： Yoshihiro UEDA ,  Naomi TAKEDA ,  Masanobu SHIRAKAWA ,  Marie TAKADA

IPC: G06F3/06 ,  G06F11/10 ,  G06F12/10

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a control circuit. The nonvolatile memory includes a plurality of storage blocks, each including a shift register. The control circuit controls writing and reading of data to and from the nonvolatile memory. The control circuit is configured to: read target data from a first storage block of the plurality of storage blocks; and write the target data read from the first storage block to a second storage block of the plurality of storage blocks, the second storage block being different from the first storage block.