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124 条记录 (耗时 0.024 秒)

    Balanced adaptive body bias control
    31.
    发明授权
    Balanced adaptive body bias control 有权
    平衡自适应体偏置控制

    公开(公告)号：US07949864B1

    公开(公告)日：2011-05-24

    申请号：US11238446

    申请日：2005-09-28

    申请人： Vjekoslav Svilan ,  James B. Burr

    发明人： Vjekoslav Svilan ,  James B. Burr

    IPC分类号： G06F1/32 ,  G06F1/24

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： Systems and methods of balanced adaptive body bias control. In accordance with a first embodiment of the present invention, a method of balanced adaptive body bias control comprises determining a desirable dynamic condition for circuitry of an integrated circuit. A first dynamic indicator corresponding to the desirable dynamic condition is accessed. Second and third dynamic indicators of the integrated circuit are accessed. A first body biasing voltage is adjusted by an increment so as to change the first dynamic indicator in the direction of the desirable dynamic condition. A second body biasing voltage is adjusted based on a relationship between the second dynamic indicator and the third dynamic indicator.

    摘要翻译： 平衡自适应体偏置控制的系统和方法。 根据本发明的第一实施例，平衡自适应体偏置控制的方法包括确定用于集成电路的电路的期望的动态条件。 访问对应于期望的动态条件的第一动态指示符。 访问集成电路的第二和第三动态指示器。 通过增量来调整第一体偏置电压，以便在期望的动态条件的方向上改变第一动态指示器。 基于第二动态指示器和第三动态指示器之间的关系来调整第二身体偏置电压。

    Raised source/drain with super steep retrograde channel
    33.
    发明授权
    Raised source/drain with super steep retrograde channel 有权
    用超级陡峭的逆行通道引起源/漏

    公开(公告)号：US07683442B1

    公开(公告)日：2010-03-23

    申请号：US11529972

    申请日：2006-09-29

    申请人： James B. Burr ,  Archisman Bagchi ,  Jawad Nasrullah

    发明人： James B. Burr ,  Archisman Bagchi ,  Jawad Nasrullah

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/26513 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/7833

    摘要： Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments in accordance with the present invention may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.

    摘要翻译： 具有超陡逆行通道的升高源/漏源的系统和方法。 根据本发明的第一实施例，在一个实施例中，半导体器件包括包括表面的衬底和设置在包括栅极氧化物厚度的表面上方的栅极氧化物。 半导体器件还包括形成在表面下方深度的超陡逆行通道区域。 深度约为栅极氧化物厚度的十至三十倍。 根据本发明的实施例可以提供比常规技术中可用的更理想的主体偏置电压到阈值电压特性。

    Systems and methods for adjusting threshold voltage
    35.
    发明授权
    Systems and methods for adjusting threshold voltage 有权
    用于调整阈值电压的系统和方法

    公开(公告)号：US07598731B1

    公开(公告)日：2009-10-06

    申请号：US11787908

    申请日：2007-04-17

    申请人： Robert Paul Masleid ,  James B. Burr

    发明人： Robert Paul Masleid ,  James B. Burr

    IPC分类号： G01R31/26

    CPC分类号： H03K19/0027 ,  G01R31/2621 ,  H03K2217/0018

    摘要： Systems and methods for adjusting threshold voltage. A threshold voltage of a transistor of an integrated circuit is measured. A bias voltage, which when applied to a body well of the transistor corrects a difference between the threshold voltage and a desired threshold voltage for the transistor, is determined. The bias voltage is encoded into non-volatile storage on the integrated circuit. The non-volatile storage can be digital and/or analog.

    摘要翻译： 用于调整阈值电压的系统和方法。 测量集成电路的晶体管的阈值电压。 当施加到晶体管的体阱时，偏置电压校正阈值电压和晶体管的期望阈值电压之间的差异。 偏置电压被编码到集成电路上的非易失性存储器中。 非易失性存储器可以是数字和/或模拟的。

    SELECTIVE COUPLING OF VOLTAGE FEEDS FOR BODY BIAS VOLTAGE IN AN INTEGRATED CIRCUIT DEVICE
    36.
    发明申请
    SELECTIVE COUPLING OF VOLTAGE FEEDS FOR BODY BIAS VOLTAGE IN AN INTEGRATED CIRCUIT DEVICE 有权
    用于集成电路设备中的身体偏置电压的电压馈电的选择性耦合

    公开(公告)号：US20080135905A1

    公开(公告)日：2008-06-12

    申请号：US12033840

    申请日：2008-02-19

    申请人： James B. Burr ,  Robert Fu

    发明人： James B. Burr ,  Robert Fu

    IPC分类号： H01L23/50 ,  G11C5/14

    CPC分类号： H01L29/0646 ,  G11C5/146 ,  H01L21/823493 ,  H01L21/823892 ,  H01L23/481 ,  H01L27/0203 ,  H01L27/0222 ,  H01L27/0928 ,  H01L29/1095 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.

    摘要翻译： 一种具有体偏置电压机构的集成电路器件。 集成电路包括设置在其中的电阻结构，用于选择性地将外部体偏置电压或电源电压耦合到偏置阱。 可以可选地提供用于与第一外部设置的销连接的第一垫。 第一个焊盘用于接收外部施加的主体偏置电压。 用于产生体偏置电压的电路可以耦合到第一焊盘，用于将体偏置电压耦合到设置在集成电路器件上的多个偏置阱。 如果没有提供外部施加的体偏置电压，则电阻结构自动将电源电压耦合到偏置阱。 电源电压可以在集成电路内部获得。

    Back-biased MOS device fabrication method
    37.
    发明授权
    Back-biased MOS device fabrication method 有权
    背偏MOS器件制造方法

    公开(公告)号：US06838328B1

    公开(公告)日：2005-01-04

    申请号：US10683957

    申请日：2003-10-10

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L21/761 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/425

    CPC分类号： H01L21/823892 ,  H01L21/761 ,  H01L21/823878 ,  H01L27/092

    摘要： A plurality of p-wells and n-wells are formed in a front side of a bulk material, and a plurality of n layers and p layers are alternately formed within the bulk material between a back side of the bulk material and the plurality of n-wells and p-wells. The plurality of n layers are electrically isolated from one another and respectively route different potentials to selected ones of the plurality of n-wells, and likewise, the plurality of p layers are electrically isolated from one another and respectively route different potentials to selected ones of the plurality of p-wells.

    Device including a resistive path to introduce an equivalent RC circuit
    39.
    发明授权
    Device including a resistive path to introduce an equivalent RC circuit 有权

    公开(公告)号：US06781213B2

    公开(公告)日：2004-08-24

    申请号：US10393534

    申请日：2003-03-20

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L2900

    CPC分类号： H01L27/092 ,  H01L27/0727 ,  H01L29/1087 ,  H01L29/8605

    摘要： Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

    Method for making die-compensated threshold tuning circuit
    40.
    发明授权
    Method for making die-compensated threshold tuning circuit 失效
    制造芯片补偿阈值调谐电路的方法

    公开(公告)号：US6048746A

    公开(公告)日：2000-04-11

    申请号：US92906

    申请日：1998-06-08

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： G01R31/26 ,  G01R31/27 ,  H01L21/66

    CPC分类号： G01R31/275 ,  G01R31/2621

    摘要： To compensate for process, activity and environmental variations in a semiconductor device, a back-bias potential tuning circuit is formed on a semiconductor die. The tuning circuit tunes a bias potential applied to the semiconductor die to maintain a predetermined ratio between a transistor on-current and a transistor off-current through at least one channel region. Then, a leakage current is measured for multiple transistors formed in the semiconductor die to determine a representative leakage of the semiconductor die. Tuning characteristics of the back-bias potential tuning circuit are then set to match the representative leakage of the semiconductor die.

    摘要翻译： 为了补偿半导体器件中的工艺，活性和环境变化，在半导体管芯上形成背偏电位调谐电路。 调谐电路调节施加到半导体管芯的偏置电位，以保持晶体管导通电流和通过至少一个沟道区域的晶体管截止电流之间的预定比率。 然后，对形成在半导体管芯中的多个晶体管测量泄漏电流，以确定半导体管芯的代表性泄漏。 然后设置背偏电位调谐电路的调谐特性以匹配半导体管芯的代表性泄漏。