公开(公告)号：US08329559B2

公开(公告)日：2012-12-11

申请号：US11737545

申请日：2007-04-19

申请人： Hideki Takeuchi ,  Emmanuel P. Quevy ,  Tsu-Jae King ,  Roger T. Howe

发明人： Hideki Takeuchi ,  Emmanuel P. Quevy ,  Tsu-Jae King ,  Roger T. Howe

IPC分类号： H01L21/46 ,  H01L21/78 ,  H01L21/301

CPC分类号： B81C1/00142 ,  B81B2201/0271 ,  B81C2201/0109 ,  Y10S438/933

摘要： In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.

摘要翻译： 在制造微机电结构（MEMS）中，在MEMS中形成窄间隙的方法包括：a）在支撑衬底的表面上沉积牺牲材料层，b）光致抗蚀剂掩模并且至少部分蚀刻牺牲材料以形成 至少一个牺牲材料刀片，c）在所述牺牲层上沉积结构层，以及d）去除包括所述牺牲材料刀片的所述牺牲层，其中所述牺牲材料刀片被去除的所述结构层中残留有窄间隙 。

公开(公告)号：US20090148480A1

公开(公告)日：2009-06-11

申请号：US11995500

申请日：2006-07-14

申请人： Nobuyuki Isshiki ,  Noboru Kamada ,  Hideki Takeuchi

发明人： Nobuyuki Isshiki ,  Noboru Kamada ,  Hideki Takeuchi

IPC分类号： A61K9/00 ,  A61P1/00

CPC分类号： A61K9/0065 ,  A61K9/2086 ,  A61K31/341 ,  A61K31/496

摘要： The invention provides a preparation which shows a satisfactory gastric residence time, has such a size that allows for easy ingestion, can quickly disintegrate after expelled from the stomach, and can be prepared readily in an industrial scale. A gastric retentive preparation having a gastric resident layer and a drug release layer is provided, wherein the gastric resident layer does not disintegrate in the stomach and disintegrates in the intestine. Preferably, the gastric resident layer has a minimum diameter of 7 mm or more as measured after stirring the preparation in the first fluid at 200 rpm at 37° C. for 15 hours under the conditions of the paddle method in the dissolution test in accordance with Japanese Pharmacopoeia and has a maximum diameter of 6 mm or less as measured after further stirring the preparation in the second fluid at 200 rpm at 37° C. for 9 hours under the same conditions.

摘要翻译： 本发明提供一种显示令人满意的胃停留时间的制剂，具有允许容易摄入的尺寸，可以在从胃排出后迅速崩解，并且可以以工业规模容易地制备。 提供了具有胃滞留层和药物释放层的胃滞留制剂，其中胃停留层在胃中不分解并在肠中分解。 优选地，胃停留层的最小直径为7mm以上，在第一流体中的制剂在200rpm下在37℃下搅拌15小时时，在桨式方法的条件下根据溶出试验按照 日本药典，并且在相同条件下，在第二流体中以200rpm在37℃下进一步搅拌制备9小时后测得的最大直径为6mm或更小。

公开(公告)号：US20060197695A1

公开(公告)日：2006-09-07

申请号：US11411143

申请日：2006-04-26

申请人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

发明人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

IPC分类号： H03M1/12

CPC分类号： H03K19/00361 ,  H03K17/162

摘要： The present invention provides an noise suppression circuit comprises an internal circuit which has a high and a low level terminals. The low level terminal is connected to a low level power supply (GND) line. The noise suppression circuit further comprises a first transistor in which one main electrode is connected to the high level terminal of the circuit, a bypass capacitor connected between the other main electrode of the first transistor and the low level power supply line, and a second transistor connected between the other main electrode of the first transistor and a high level power supply (VDD) line. The first transistor is conductive when the internal circuit is active, and is not conductive when the internal circuit is inactive. The second transistor is not conductive when the internal circuit is active, and is conductive when the internal circuit is inactive. Moreover, a communication circuit for setting the number of data buses to be newly added to be less than two times a transmission on data, then encoding the data to be sent 80 as to make the numbers of “0” and “1” in the data to be sent through the data buses equal to each other and accordingly reducing the increase of the number of the data buses to a minimum and thereby suppressing the common phase power supply noise is provided. A communication apparatus comprising the communication circuit is also provided. Furthermore, the bypass capacitor C for noise suppression circuit is formed in an empty space in a ASIC. A polysilicon layer constituting one electrode of the bypass capacitor is formed in the substrate contact region formed between basic cells regularly arranged, each including a plurality of nMOS and pMOS transistors. This bypass capacitor C is connected between the high and the low level power supply lines to reduce the current running through the power supply line to suppress the EMI noise.

公开(公告)号：US07095662B2

公开(公告)日：2006-08-22

申请号：US11075669

申请日：2005-03-10

申请人： Hideki Takeuchi ,  Takuya Fujimoto

发明人： Hideki Takeuchi ,  Takuya Fujimoto

IPC分类号： G11C7/00

CPC分类号： G11C16/10 ,  G11C29/789

摘要： A semiconductor memory device including: a first memory cell array including a plurality of memory cells, a first switch circuit for transferring data to be programmed to at least one of the plurality of memory cells arranged in the first memory cell array, a latch circuit for latching the data transferred from the first switch circuit, a first write selector circuit for transferring the data transferred from the latch circuit, a first bit line connected to at least one of the plurality of memory cells and receiving the data transferred from the first write selector circuit, a second memory cell array including a plurality of memory cells that are different from the plurality of memory cells arranged in the first memory cell array, a second switch circuit for transferring data to be programmed to at least one of the plurality of memory cells arranged in the second memory cell array, a second write selector circuit connected to the second switch circuit and transferring the data transferred from the second switch circuit, and a second bit line connected to at least one of the plurality of memory cells arranged in the second memory cell array.

摘要翻译： 一种半导体存储器件，包括：第一存储单元阵列，包括多个存储单元;第一开关电路，用于将被编程的数据传送到布置在第一存储单元阵列中的多个存储单元中的至少一个;锁存电路， 锁存从第一开关电路传送的数据，用于传送从锁存电路传送的数据的第一写选择器电路，连接到多个存储单元中的至少一个的第一位线，并接收从第一写选择器传送的数据 电路，包括与布置在第一存储单元阵列中的多个存储单元不同的多个存储单元的第二存储单元阵列;第二开关电路，用于将要编程的数据传送到多个存储单元中的至少一个存储单元 布置在第二存储单元阵列中，第二写选择器电路连接到第二开关电路并传送数据 并且连接到布置在第二存储单元阵列中的多个存储单元中的至少一个的第二位线。

公开(公告)号：US06790295B2

公开(公告)日：2004-09-14

申请号：US10184366

申请日：2002-06-25

申请人： Toyotaka Kinoshita ,  Hiromi Sumi ,  Shingo Nakayama ,  Yoshinori Takeda ,  Motoharu Yamagoshi ,  Hideki Takeuchi

发明人： Toyotaka Kinoshita ,  Hiromi Sumi ,  Shingo Nakayama ,  Yoshinori Takeda ,  Motoharu Yamagoshi ,  Hideki Takeuchi

IPC分类号： C23C846

CPC分类号： F16C33/12 ,  C23C8/80 ,  F16C2204/60

摘要： A method of improving wear-resistance and anti-seizing properties of slide surface of machineries, such as outer slide surfaces of piston pins of vehicle engines, wherein slide surfaces of iron or steel base materials of machineries are first processed carburizing, then the carburized surfaces are plated with chromium, and next the chromium-plated surfaces undergo impulses fine peening to produce lubricant-retaining cavities on the slide surfaces, which include fine cavities in the form of depressions in the chromium-plating layer and relatively large cavities produced by exfoliation of the chromium-plating layer.

摘要翻译： 首先，对车辆的发动机的活塞销的外侧滑动面等机械的滑动面的耐磨性和防卡住性提高的方法进行了改进，其中，对机械的钢铁基材的滑动面进行了第一次的渗碳处理， 镀铬，接下来的镀铬表面经过脉冲精细喷丸处理以在滑动表面上产生润滑剂保持腔，其包括镀铬层中的凹陷形式的细小空腔和通过剥离产生的相对较大的空腔 镀铬层。

公开(公告)号：US06502122B1

公开(公告)日：2002-12-31

申请号：US09146239

申请日：1998-09-03

申请人： Hideki Takeuchi

发明人： Hideki Takeuchi

IPC分类号： G06F900

CPC分类号： G06F9/52

摘要： The method of the present invention comprises the steps of: provisionally updating a resource through a first transaction program and locking the resource; determining if a second transaction program generates a request to update the resource which has been locked because of the provisional update through the first transaction program; making the second transaction program exclusively wait and reproducing a third transaction program having an internal status identical to that of the second transaction program when the second transaction program generates the update request; providing a virtual resource having an original status before the provisional update through the first transaction program; provisionally updating the virtual resource through the third transaction program without exclusive wait; and rolling back and closing the exclusively waiting second transaction program and executing commit in the reproduced third transaction program when rollback of the first transaction program is executed due to an abnormal situation detected in the first transaction program.

摘要翻译： 本发明的方法包括以下步骤：通过第一事务程序临时更新资源并锁定资源; 确定第二交易程序是否由于通过第一交易程序的临时更新而产生更新已被锁定的资源的请求; 当所述第二交易程序生成所述更新请求时，使所述第二交易程序专门等待和再现具有与所述第二交易程序的内部状态相同的内部状态的第三交易程序; 提供通过所述第一交易程序在所述临时更新之前具有原始状态的虚拟资源; 通过第三个事务程序暂时更新虚拟资源，而不需要排除等待; 并且当由于在第一交易程序中检测到的异常情况执行第一交易程序的回滚时，回滚和关闭专门等待的第二交易程序并且在再现的第三交易程序中执行提交。

公开(公告)号：US06461912B2

公开(公告)日：2002-10-08

申请号：US09817142

申请日：2001-03-27

申请人： Hideki Takeuchi ,  Hirohiko Izumi

发明人： Hideki Takeuchi ,  Hirohiko Izumi

IPC分类号： H01L218242

CPC分类号： H01L27/10855 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10885 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor storage device, an access transistor, which has a gate electrode and a pair of impurity diffusion layers, is formed at a device activation region defined by a device isolation structure of a semiconductor substrate. A first insulating film, which has a first contact hole for exposing a portion of the surface of one of the pair of impurity diffusion layers, is formed over the access transistor. A protective film, which has a second contact hole formed on the first contact hole, is formed on the first insulating film. A second insulating film is formed on the side wall faces of the first and second contact holes. A memory capacitor has a lower electrode and an upper part electrode which are opposed each other and are capacitive-coupled through a dielectric film. The lower electrode is filled inside the first and second contact holes to be formed in an island-like shape on the first insulating film through the protective film so as to be electrically connected with the one of the pair of impurity diffusion layers. Each of the first and second contact holes has a diameter which is made smaller by an existence of the second insulating film than a minimum dimension determined by an exposure limit in a photolithography.

摘要翻译： 在半导体存储装置中，在由半导体衬底的器件隔离结构限定的器件激活区域处形成具有栅电极和一对杂质扩散层的存取晶体管。 在该存取晶体管的上方形成第一绝缘膜，该第一绝缘膜具有用于暴露该对杂质扩散层之一的表面的一部分的第一接触孔。 在第一绝缘膜上形成有形成在第一接触孔上的第二接触孔的保护膜。 第二绝缘膜形成在第一和第二接触孔的侧壁面上。 记忆电容器具有彼此相对并且通过电介质膜电容耦合的下部电极和上部电极。 下部电极填充在第一和第二接触孔的内部，以通过保护膜在第一绝缘膜上形成为岛状，以便与一对杂质扩散层电连接。 第一和第二接触孔中的每一个具有通过第二绝缘膜的存在使得比通过光刻中的曝光极限确定的最小尺寸更小的直径。

公开(公告)号：US06392264B2

公开(公告)日：2002-05-21

申请号：US09110252

申请日：1998-07-06

申请人： Hideki Takeuchi ,  Hirohiko Izumi

发明人： Hideki Takeuchi ,  Hirohiko Izumi

IPC分类号： H01L2978

CPC分类号： H01L28/91 ,  H01L21/76895

摘要： A semiconductor memory device has access transistors with a gate and a pair of impurity diffusion layers formed on a semiconductor substrate and memory capacitors with a storage node electrode and a cell plate electrode. The electrodes are connected to each other via a capacitive insulating layer made of a ferroelectric material. The storage node electrode has a surface covered with the capacitive insulating layer and is formed in a shape of column on one of the pair of impurity diffusion layers in a hole formed from an inter-layer insulating film covering the access transistor to the one of the pair of impurity diffusion layers. A upper surface of the column does not exceed the inter-layer insulating film. The storage node electrode formed in the hole face the cell plate electrode via the inter-layer insulating film.

摘要翻译： 半导体存储器件具有存取晶体管，其具有形成在半导体衬底上的栅极和一对杂质扩散层，以及具有存储节点电极和单元板电极的存储电容器。 电极通过由铁电体材料制成的电容绝缘层彼此连接。 存储节点电极具有被电容绝缘层覆盖的表面，并且在由覆盖存取晶体管的层间绝缘膜形成的孔中的一对杂质扩散层中的一个上形成为列的形状 一对杂质扩散层。 柱的上表面不超过层间绝缘膜。 形成在孔中的存储节点电极经由层间绝缘膜与电池板电极相对。

公开(公告)号：US5966521A

公开(公告)日：1999-10-12

申请号：US853908

申请日：1997-05-09

申请人： Hideki Takeuchi ,  Mototaka Kuribayashi ,  Junichi Tsujimoto ,  Kentaro Kuroiwa ,  Yasuhiro Tonooka

发明人： Hideki Takeuchi ,  Mototaka Kuribayashi ,  Junichi Tsujimoto ,  Kentaro Kuroiwa ,  Yasuhiro Tonooka

IPC分类号： G01R31/28 ,  G06F17/50 ,  H01L21/82

CPC分类号： G06F17/5031

摘要： The present invention provide a system and a method for analyzing the static timing for LSIs which involves rather a small number of false paths contained in output results and also which reduces the processing time required. A static-timing analysis technique according to the present invention comprises a net-list input step S110 which inputs per-transistor basis connection information, to construct an internal data structure for analysis; an expected-value check step S120 which checks, against the above-mentioned internal data structure, each node on whether its expected values may be a high-impedance state; a signal-flow direction narrow-down step S130 which narrows down the directions in which the transistor signal may flow, based on the obtained expected values; a division step S140 which divides a sequential circuit into units consisting of only combinational sub-circuits; a path search step S150 which searches paths for each of thus divided units; and an output step S170 which outputs the obtained results.

摘要翻译： 本发明提供了一种用于分析LSI的静态定时的系统和方法，其涉及输出结果中包含的少量虚路径，并且还减少了所需的处理时间。 根据本发明的静态时序分析技术包括输入每晶体管基连接信息的网络列表输入步骤S110，以构建用于分析的内部数据结构; 预测值检查步骤S120，其针对上述内部数据结构检查每个节点关于其预期值是否可能是高阻抗状态; 基于所获得的期望值，使晶体管信号可能流过的方向变窄的信号流动方向缩小步骤S130; 将顺序电路分为仅由组合子电路组成的单元的分割步骤S140; 路径搜索步骤S150，其针对每个这样划分的单元的路径进行搜索; 以及输出步骤S170，其输出所获得的结果。

公开(公告)号：US5693223A

公开(公告)日：1997-12-02

申请号：US802420

申请日：1997-02-18

申请人： Saichi Yamada ,  Hideki Takeuchi ,  Kazunari Yamada ,  Tsuyoshi Majima

发明人： Saichi Yamada ,  Hideki Takeuchi ,  Kazunari Yamada ,  Tsuyoshi Majima

IPC分类号： B01D15/08 ,  G01N30/02 ,  G01N30/52 ,  G01N30/60 ,  G01N30/88

CPC分类号： G01N30/6004 ,  B01D15/08 ,  G01N30/603 ,  G01N30/6052 ,  G01N30/6091 ,  G01N2030/027 ,  G01N2030/524 ,  G01N2030/8813 ,  G01N2030/8822 ,  G01N2030/8831 ,  G01N30/02 ,  G01N30/6017 ,  G01N30/6082

摘要： A column for low pressure-high speed liquid chromatography, including a column body being made of a transparent or translucent plastic and having a column chamber, said column body having one end opened and the other provided with an outflow opening, a pair of upstream and downstream filters for shutting a granular filler inside said column chamber, and a head portion being made of a plastic and detachably being fitted to said one open end of the column body and having an inflow through opening communicating with interior of said column body. A column device includes the column and a method for using the column device are also disclosed for low pressure-high speed liquid chromatography.

摘要翻译： 一种用于低压 - 高速液相色谱的柱，包括柱体，由透明或半透明的塑料制成并具有柱室，所述柱体的一端打开，另一端设有流出开口，一对上游和 用于在所述柱室内关闭颗粒填料的下游过滤器，以及头部，其由塑料制成并且可拆卸地装配到所述柱体的所述一个开口端，并具有与所述柱体内部连通的流入通孔。 包括柱的柱装置和用于低压 - 高速液相色谱的柱装置的方法也被公开。