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    Memory device refresh
    31.
    发明授权
    Memory device refresh 有权
    内存设备刷新

    公开(公告)号：US09053811B2

    公开(公告)日：2015-06-09

    申请号：US13609655

    申请日：2012-09-11

    申请人： Paul W. Coteus ,  Douglas J. Joseph ,  Kyu-hyoun Kim

    发明人： Paul W. Coteus ,  Douglas J. Joseph ,  Kyu-hyoun Kim

    IPC分类号： G11C7/00 ,  G11C11/406

    CPC分类号： G11C11/40611 ,  G06F13/1668 ,  Y02D10/14

    摘要： According to one embodiment of the present invention, a method for refreshing memory includes receiving a synchronization command at a memory device. An internal refresh timer is reset within the memory device based on receiving the synchronization command. An internal refresh trigger is generated within the memory device based on the internal refresh timer reaching a predetermined value. A refresh of a memory array is performed within the memory device based on the internal refresh trigger.

    摘要翻译： 根据本发明的一个实施例，一种用于刷新存储器的方法包括在存储器件处接收同步命令。 基于接收到同步命令，内存刷新定时器在存储器设备内重置。 基于内部刷新定时器达到预定值，在存储器件内产生内部刷新触发。 基于内部刷新触发，在存储器装置内执行刷新存储器阵列。

    ADVANCED MEMORY DEVICE HAVING REDUCED POWER AND IMPROVED PERFORMANCE
    33.
    发明申请
    ADVANCED MEMORY DEVICE HAVING REDUCED POWER AND IMPROVED PERFORMANCE 有权
    具有降低功率的高级存储器件和改进的性能

    公开(公告)号：US20100220536A1

    公开(公告)日：2010-09-02

    申请号：US12394804

    申请日：2009-02-27

    申请人： Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Kenneth L. Wright

    发明人： Paul W. Coteus ,  Daniel M. Dreps ,  Kevin C. Gower ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Kenneth L. Wright

    IPC分类号： G11C7/00 ,  G11C8/18

    CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C8/12 ,  Y02D10/14

    摘要： A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.

    摘要翻译： 一种包括存储数据的存储器阵列，可变延迟控制器，无源可变延迟电路和输出驱动器的存储器件。 可变延迟控制器在存储器件的操作期间周期性地从存储器件外部的第一源接收延迟命令，并且响应于接收的延迟命令而输出延迟指令位。 无源可变延迟电路从存储器件外部的第二源接收时钟，从可变延迟控制器接收延迟指令位，产生与由延迟指令位确定的接收时钟具有时间关系的延迟时钟，以及 输出延迟时钟。 输出驱动器从存储器阵列和延迟时钟接收数据，并且响应于延迟的时钟一次输出数据。

    STACKED MEMORY ARRAY
    34.
    发明申请
    STACKED MEMORY ARRAY 审中-公开
    堆叠内存阵列

    公开(公告)号：US20100121994A1

    公开(公告)日：2010-05-13

    申请号：US12267646

    申请日：2008-11-10

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus

    IPC分类号： G06F3/00 ,  G06F13/28

    CPC分类号： G06F13/1684 ,  G11C5/02 ,  G11C5/063 ,  Y02D10/14

    摘要： A memory subsystem, array controller, method, and design structure are provided for a stacked memory array. The memory subsystem includes an array controller and at least one memory array. The array controller includes a primary and secondary buffer interface to communicate with a memory controller via a cascade interconnected bus. The array controller also includes an array access controller to process memory access commands received via one of the primary and secondary buffer interfaces. The at least one memory array includes a memory cell array die separately packaged with respect to the array controller and coupled to the array controller in a stacked configuration via memory core data lines using through silicon vias (TSVs).

    摘要翻译： 为堆叠的存储器阵列提供存储器子系统，阵列控制器，方法和设计结构。 存储器子系统包括阵列控制器和至少一个存储器阵列。 阵列控制器包括主缓冲器和辅助缓冲器接口，用于经由级联的互连总线与存储器控制器进行通信。 阵列控制器还包括一个阵列访问控制器，用于处理通过主缓冲区和辅助缓冲区接口之一接收的存储器访问命令。 所述至少一个存储器阵列包括相对于阵列控制器单独封装的存储单元阵列，并且经由存储器核心数据线通过硅通孔（TSV）以堆叠配置耦合到阵列控制器。

    System for generating a multiple phase clock
    35.
    发明授权
    System for generating a multiple phase clock 失效
    用于产生多相时钟的系统

    公开(公告)号：US07683725B2

    公开(公告)日：2010-03-23

    申请号：US11838282

    申请日：2007-08-14

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus

    IPC分类号： H03K3/03

    CPC分类号： H03K3/0315 ,  H03K5/15026 ,  H03K5/1506

    摘要： A system for generating a multiple phase clock is provided. The system includes a ring oscillator structure for generating multiple phases. The structure includes two or more unit oscillators, each unit oscillator implemented by a ring oscillator having M stages. The structure also includes a horizontal loop coupling the two or more unit oscillators to generate multiple phases. The number of phases generated is equal to the product of the number of unit oscillators and M. Another structure generates multiple phases using a multi-dimensional oscillator including ring oscillators constructed as vertical and horizontal loops with shared elements between the oscillators. A memory system includes a ring oscillator structure with vertical and horizontal loops, the ring oscillator structure receiving an input clock and outputting a multiple phase clock to one or more of a memory controller, memory devices and a memory interface device.

    摘要翻译： 提供了一种用于产生多相时钟的系统。 该系统包括用于产生多相的环形振荡器结构。 该结构包括两个或多个单元振荡器，每个单位振荡器由具有M级的环形振荡器实现。 该结构还包括耦合两个或多个单元振荡器以产生多个相位的水平环路。 产生的相数等于单位振荡器和M的数量的乘积。另一种结构使用多维振荡器产生多个相位，该多维振荡器包括环形振荡器，其被构造为在振荡器之间具有共享元件的垂直和水平回路。 存储器系统包括具有垂直和水平环路的环形振荡器结构，环形振荡器结构接收输入时钟并将多相时钟输出到存储器控制器，存储器件和存储器接口器件中的一个或多个。

    SYSTEM AND METHOD FOR PROVIDING A NON-POWER-OF-TWO BURST LENGTH IN A MEMORY SYSTEM
    36.
    发明申请
    SYSTEM AND METHOD FOR PROVIDING A NON-POWER-OF-TWO BURST LENGTH IN A MEMORY SYSTEM 有权
    用于在存储器系统中提供非功率的两个BURST长度的系统和方法

    公开(公告)号：US20090251988A1

    公开(公告)日：2009-10-08

    申请号：US12061045

    申请日：2008-04-02

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Warren E. Maule ,  Kenneth L. Wright

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Warren E. Maule ,  Kenneth L. Wright

    IPC分类号： G11C8/00

    CPC分类号： G11C5/00 ,  G11C7/1018

    摘要： A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices.

    摘要翻译： 提供了一种用于非二次突发长度的存储器系统，存储器接口装置和方法。 存储器系统包括具有非二次突发长度逻辑的多个存储器件和包括非二次突发长度生成逻辑的存储器接口器件。 非功率二突发长度生成逻辑从两个功率值扩展突发长度，以将错误检测码插入到存储器接口设备和多个存储器件之间的数据线上的突发中。

    System for providing read clock sharing between memory devices
    37.
    发明授权
    System for providing read clock sharing between memory devices 失效
    用于在存储器件之间提供读取时钟共享的系统

    公开(公告)号：US07593288B2

    公开(公告)日：2009-09-22

    申请号：US11959711

    申请日：2007-12-19

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus

    IPC分类号： G11C7/00

    CPC分类号： G11C5/04 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03L7/07 ,  H03L7/0812

    摘要： A system for providing read clock sharing between memory devices. The system includes a memory device having an external clock receiver, a read clock receiver, and a phase comparator. The phase comparator synchronizes an internal read clock generated at the memory device. The phase comparator additionally synchronizes one of an external clock received by the external clock receiver and an external read clock received by the read clock receiver. The results of the synchronizing are utilized to refresh the internal read clock. The memory device also includes a mechanism, a read clock driver and a mode register fit. The mechanism is utilized to select between the external clock and the external read clock as input to the phase comparator. The read clock driver outputs the internal read clock generated at the memory device to a read clock output pin. The mode register bit controls the selection of the mechanism, the enabling and disabling of the read clock receiver and the enabling and disabling of the read clock driver.

    摘要翻译： 一种用于在存储器件之间提供读时钟共享的系统。 该系统包括具有外部时钟接收器，读取时钟接收器和相位比较器的存储器件。 相位比较器同步存储器件产生的内部读时钟。 相位比较器还将由外部时钟接收器接收到的外部时钟和由读取时钟接收器接收到的外部读取时钟之一进行同步。 利用同步的结果刷新内部读时钟。 存储器件还包括机构，读时钟驱动器和模式寄存器配合。 该机制用于在外部时钟和外部读取时钟之间选择作为相位比较器的输入。 读时钟驱动器将存储器件产生的内部读时钟输出到读时钟输出引脚。 模式寄存器位控制机制的选择，读时钟接收器的使能和禁止以及读时钟驱动器的使能和禁止。

    SYSTEM FOR PROVIDING OPEN-LOOP QUADRATURE CLOCK GENERATION
    38.
    发明申请
    SYSTEM FOR PROVIDING OPEN-LOOP QUADRATURE CLOCK GENERATION 失效
    用于提供开环时钟产生的系统

    公开(公告)号：US20080285697A1

    公开(公告)日：2008-11-20

    申请号：US11749409

    申请日：2007-05-16

    申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Daniel M. Dreps

    发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Daniel M. Dreps

    IPC分类号： H03D3/24

    CPC分类号： H03K5/151 ,  H03K5/13 ,  H03K2005/00052 ,  H03K2005/00234

    摘要： A system for providing open-loop quadrature clock generation. The system is implemented by a ring oscillator structure that includes input inverters for receiving an input clock, forward direction loop inverters, backward direction loop inverters, one or more outputs, and cross-coupled latches connected between any two opposite nodes.

    摘要翻译： 一种用于提供开环正交时钟生成的系统。 该系统由环形振荡器结构实现，该环形振荡器结构包括用于接收输入时钟的输入反相器，正向环路逆变器，反向环路逆变器，一个或多个输出以及连接在任何两个相对节点之间的交叉耦合的锁存器。

    Synchronous rectifier gate drive timing to compensate for transformer leakage inductance
    39.
    发明授权
    Synchronous rectifier gate drive timing to compensate for transformer leakage inductance 有权
    同步整流栅驱动定时补偿变压器漏电感

    公开(公告)号：US08358522B2

    公开(公告)日：2013-01-22

    申请号：US12836933

    申请日：2010-07-15

    申请人： Paul W. Coteus ,  Andrew Ferencz

    发明人： Paul W. Coteus ,  Andrew Ferencz

    IPC分类号： H02M5/42

    CPC分类号： H02M3/33592 ,  H02M2001/0048 ,  Y02B70/1475 ,  Y02B70/1491

    摘要： An apparatus for providing synchronous rectifier gate drive timing is described. The apparatus includes circuitry to receive a first signal. The apparatus also includes circuitry to generate a second signal by modifying the first signal to delay a transition from high to low for a non-zero overlap duration. An output to apply an inverse of the first signal as a gate drive timing of at least a first transistor and to apply the second signal as a gate drive timing of at least a second transistor, where the first transistor is a part of a primary side of a full-bridge synchronous rectifier and the second transistor is a part of a secondary side of the full-bridge synchronous rectifier is also included. The second signal and the inverse of the first signal are high during the overlap duration. Methods and program storage devices are also disclosed.

    摘要翻译： 描述了一种用于提供同步整流栅驱动定时的装置。 该装置包括用于接收第一信号的电路。 该装置还包括通过修改第一信号以在非零重叠持续时间内将从高转变为低的过渡来产生第二信号的电路。 用于将第一信号的反相作为至少第一晶体管的栅极驱动定时的输出，并施加第二信号作为至少第二晶体管的栅极驱动定时，其中第一晶体管是初级侧的一部分 的全桥同步整流器，而第二晶体管也是全桥同步整流二次侧的一部分。 第二信号和第一信号的反相在重叠期间是高的。 还公开了方法和程序存储装置。