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31.发明授权Amplifier with reduced on/off transient and multi-point offset compensation 有权具有减小的开/关瞬变和多点偏移补偿的放大器公开(公告)号：US08482347B2
公开(公告)日：2013-07-09
申请号：US12930487
申请日：2011-01-07
申请人： Iuri Mehr , Sherif Galal , Todd L. Brooks
发明人： Iuri Mehr , Sherif Galal , Todd L. Brooks
IPC分类号： H03F1/14
CPC分类号： H03F3/187 , H03F1/305 , H03F3/72 , H03F2200/411 , H03F2203/7236
摘要： Disclosed is an amplifier designed to substantially reduce an ON/OFF transient. The amplifier comprises a drive block that includes a pre-driver and an output stage. The amplifier also comprises a bypass circuit that is coupled to an output of the pre-driver. The bypass circuit of the amplifier is selectively activated to reduce the ON/OFF transient. The bypass circuit may comprise an auxiliary output stage that can be coupled to provide selective activation. The amplifier may also be configured to provide multi-point offset compensation. Also disclosed is a related method. The amplifier and the related method may be incorporated into an audio amplifier used in a cellular telephone or other mobile audio device.
摘要翻译： 公开了一种设计用于大大减少ON / OFF瞬变的放大器。 该放大器包括一个包括一个预驱动器和一个输出级的驱动块。 放大器还包括耦合到预驱动器的输出的旁路电路。 选择性地激活放大器的旁路电路以减少ON / OFF瞬变。 旁路电路可以包括可以耦合以提供选择性激活的辅助输出级。 放大器还可以被配置为提供多点偏移补偿。 还公开了相关方法。 放大器和相关方法可以结合到用于蜂窝电话或其它移动音频设备的音频放大器中。
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32.发明授权Method and system for detecting and identifying electronic accessories or peripherals 有权用于检测和识别电子配件或外围设备的方法和系统公开(公告)号：US08452428B2
公开(公告)日：2013-05-28
申请号：US12268305
申请日：2008-11-10
CPC分类号： G06F13/4072
摘要： Aspects of a method and system for detecting and identifying electronic accessories or peripherals utilizing a hardware audio CODEC are provided. In this regard, a hardware audio CODEC may be operable to compare one or more voltages on one or more biased pins of an accessory or peripheral port to one or more reference voltages and generate one or more digital representations of the one or more voltages on the biased one or more pins. An accessory or peripheral attached to the accessory or peripheral port may be identified based on the comparison and/or the generated one or more digital representations. The one or more bias voltages may be controlled based on a result of the comparison and/or the generated digital representations. The one or more bias voltages may be reduced after an attached accessory or peripheral has been identified.
摘要翻译： 提供了利用硬件音频CODEC来检测和识别电子附件或外围设备的方法和系统的方面。 在这方面，硬件音频编解码器可以用于将附件或外围端口的一个或多个偏置引脚上的一个或多个电压与一个或多个参考电压进行比较，并且生成一个或多个电压的一个或多个数字表示 偏置一个或多个引脚。 可以基于比较和/或所生成的一个或多个数字表示来识别附接到附件或外围端口的附件或外围设备。 可以基于比较的结果和/或所生成的数字表示来控制一个或多个偏置电压。 在附加附件或外围设备被识别之后，可以减小一个或多个偏置电压。
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公开(公告)号：US07933295B2
公开(公告)日：2011-04-26
申请号：US09949811
申请日：2001-09-12
申请人： James C. Thi , Theodore F. Rabenko , David Hartman , Robert M. Lukas , Kenneth J. Unger , Ramin Borazjani , Shane P. Lansing , Robert J. Lee , Todd L. Brooks , Kevin L. Miller
发明人： James C. Thi , Theodore F. Rabenko , David Hartman , Robert M. Lukas , Kenneth J. Unger , Ramin Borazjani , Shane P. Lansing , Robert J. Lee , Todd L. Brooks , Kevin L. Miller
CPC分类号： H04M7/0087 , H04B3/23 , H04B3/234 , H04J3/0632 , H04J3/0638 , H04L12/2801 , H04L12/2834 , H04L12/5692 , H04L12/66 , H04L29/06027 , H04L65/1069 , H04M7/006 , H04M7/125 , H04N7/10 , H04N21/2383 , H04N21/4382
摘要： A network gateway is configured to facilitate on line and off line bi-directional communication between a number of near end data and telephony devices with far end data termination devices via a hybrid fiber coaxial network and a cable modem termination system. The described network gateway combines a QAM receiver, a transmitter, a DOCSIS MAC, a CPU, a voice and audio processor, a voice synchronizer, an Ethernet MAC, and a USB controller to provide high performance and robust operation.
摘要翻译： 网络网关被配置为通过混合光纤同轴网络和电缆调制解调器终端系统来促进多个近端数据与具有远端数据终端设备的电话设备之间的在线和离线双向通信。 所描述的网络网关组合了QAM接收机，发射机，DOCSIS MAC，CPU，语音和音频处理器，语音同步器，以太网MAC和USB控制器，以提供高性能和鲁棒的操作。
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公开(公告)号：US07126377B2
公开(公告)日：2006-10-24
申请号：US11355174
申请日：2006-02-16
IPC分类号： H03K19/0175
CPC分类号： H03F1/3205 , H03F3/005 , H03F3/45475 , H03F3/505 , H03F2200/168 , H03F2200/331 , H03F2200/417 , H03F2200/453 , H03F2203/45101 , H03F2203/5031
摘要： A source-follower transistor based buffer provides high linearity. A replica transistor is used to generate a replica voltage substantially equal to the output voltage of the buffer. The replica voltage is level shifted by a level shift circuit and applied at the drain of the source-follower transistor to improve the linearity of the buffer. The buffer may be used in conjunction with a switched-capacitor sampling circuit. A damping circuit may be used to reduce charge glitches due to sampling. The damping circuit may be a low pass filter. The buffer may be used in an interface circuit that produces an output signal from an input signal and controls the level of the output signal.
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35.发明授权Computer program product for mismatched shaping of an oversampled converter 失效用于过采样转换器不匹配整形的计算机程序产品公开(公告)号：US06930626B2
公开(公告)日：2005-08-16
申请号：US10893994
申请日：2004-07-20
申请人： Todd L. Brooks , David S. P. Ho , Kevin L. Miller , Eric Fogleman
发明人： Todd L. Brooks , David S. P. Ho , Kevin L. Miller , Eric Fogleman
摘要： Methods and apparatuses for spectrally shaping mismatch errors in a multi-bit digital to analog converter (DAC). In an embodiment, the multi-bit DAC is constructed from K separate multi-element sub-DACs, where K and the number of elements in each sub-DAC are each preferably greater than two. A received digital input code is split into a set of K sub-codes corresponding to the digital input code. The set of K sub-codes can have one of at least N different sub-code orders that specify an order of each of the K sub-codes with respect to one another, where N>2. A sum of the K sub-codes equals the digital input code. One of the at least N different sub-code orders is selected using a shuffling algorithm. Then, each sub-code in the set of K sub-codes is output in accordance with the selected sub-code order.
摘要翻译： 用于在多位数模转换器（DAC）中频谱整形失配误差的方法和装置。 在一个实施例中，多位DAC由K个分离的多元件子DAC构成，其中K和每个子DAC中的元件数量优选大于2。 接收的数字输入码被分割成与数字输入码相对应的一组K个子码。 所述K个子代码集合可以具有至少N个不同的子代码顺序中的一个，其指定相对于彼此的K个子代码中的每一个的顺序，其中N≥2。 K个子码的总和等于数字输入码。 使用混洗算法来选择至少N个不同的子代码顺序之一。 然后，根据所选择的子代码顺序输出K个子代码集合中的每个子代码。
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36.发明授权System and method for performing digital-to-analog conversion using a sigma-delta modulator 失效使用Σ-Δ调制器执行数模转换的系统和方法公开(公告)号：US06816097B2
公开(公告)日：2004-11-09
申请号：US10379593
申请日：2003-03-06
申请人： Todd L. Brooks , David S. P. Ho , Kevin L. Miller
发明人： Todd L. Brooks , David S. P. Ho , Kevin L. Miller
IPC分类号： H03M300
摘要： The present invention is directed to a sigma-delta digital to analog converted (DAC) including a digital-sigma delta modulator, a decimation filter, and a multi-bit DAC. The digital sigma-delta modulator receives a digital input signal and produces a quantized digital signal therefrom. The decimation filter receives the quantized digital signal and produces a decimated digital signal therefrom. The multi-bit DAC receives the decimated digital signal and produces an analog output signal therefrom. The analog output signal is representative of the digital input signal.
摘要翻译： 本发明涉及一种包括数字Σ-Δ调制器，抽取滤波器和多位DAC的Σ-Δ数模转换（DAC）。 数字Σ-Δ调制器接收数字输入信号并从其产生量化的数字信号。 抽取滤波器接收量化的数字信号并从其产生抽取的数字信号。 多位DAC接收抽取的数字信号并从其产生模拟输出信号。 模拟输出信号代表数字输入信号。
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37.发明授权公开(公告)号：US06771199B2
公开(公告)日：2004-08-03
申请号：US10408446
申请日：2003-04-08
申请人： Todd L. Brooks , David S. P. Ho , Kevin L. Miller , Eric Fogleman
发明人： Todd L. Brooks , David S. P. Ho , Kevin L. Miller , Eric Fogleman
IPC分类号： H03M166
摘要： Methods and apparatuses for spectrally shaping mismatch errors in a multi-bit digital to analog converter (DAC). In an embodiment, the multi-bit DAC is constructed from K separate multi-element sub-DACs, where K and the number of elements in each sub-DAC are each preferably greater than two. A received digital input code is split into a set of K sub-codes corresponding to the digital input code. The set of K sub-codes can have one of at least N different sub-code orders that specify an order of each of the K sub-codes with respect to one another, where N>2. A sum of the K sub-codes equals the digital input code. One of the at least N different sub-code orders is selected using a shuffling algorithm. Then, each sub-code in the set of K sub-codes is output in accordance with the selected sub-code order.
摘要翻译： 用于在多位数模转换器（DAC）中频谱整形失配误差的方法和装置。 在一个实施例中，多位DAC由K个分离的多元件子DAC构成，其中K和每个子DAC中的元件数量优选大于2。 接收的数字输入码被分割成与数字输入码相对应的一组K个子码。 所述K个子代码集合可以具有至少N个不同的子代码顺序中的一个，其指定相对于彼此的K个子代码中的每一个的顺序，其中N≥2。 K个子码的总和等于数字输入码。 使用混洗算法来选择至少N个不同的子代码顺序之一。 然后，根据所选择的子代码顺序输出K个子代码集合中的每个子代码。
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公开(公告)号：US06628218B2
公开(公告)日：2003-09-30
申请号：US09949807
申请日：2001-09-12
申请人： Todd L. Brooks , David S. P. Ho , Kevin L. Miller , Eric Fogleman
发明人： Todd L. Brooks , David S. P. Ho , Kevin L. Miller , Eric Fogleman
IPC分类号： H03M300
摘要： Methods and apparatuses for spectrally shaping mismatch errors in a multi-bit digital to analog converter (DAC). In an embodiment, the multi-bit DAC is constructed from K separate multi-element sub-DACs, where K and the number of elements in each sub-DAC are each preferably greater than two. A received digital input code is split into a set of K sub-codes corresponding to the digital input code. The set of K sub-codes can have one of at least N different sub-code orders that specify an order of each of the K sub-codes with respect to one another, where N>2. A sum of the K sub-codes equals the digital input code. One of the at least N different sub-code orders is selected using a shuffling algorithm. Then, each sub-code in the set of K sub-codes is output in accordance with the selected sub-code order.
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公开(公告)号：US06531973B2
公开(公告)日：2003-03-11
申请号：US09949814
申请日：2001-09-12
申请人： Todd L. Brooks , David S. P. Ho , Kevin L. Miller
发明人： Todd L. Brooks , David S. P. Ho , Kevin L. Miller
IPC分类号： H03M300
摘要： The present invention is directed to a sigma-delta digital to analog converted (DAC) including a digital-sigma delta modulator, a decimation filter, and a multi-bit DAC. The digital sigma-delta modulator receives a digital input signal and produces a quantized digital signal therefrom. The decimation filter receives the quantized digital signal and produces a decimated digital signal therefrom. The multi-bit DAC receives the decimated digital signal and produces an analog output signal therefrom. The analog output signal is representative of the digital input signal.
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公开(公告)号：US20120056672A1
公开(公告)日：2012-03-08
申请号：US12807403
申请日：2010-09-03
IPC分类号： H03F3/16
CPC分类号： H03F3/211 , H03F1/301 , H03F3/3022 , H03F2200/375 , H03F2200/453 , H03F2203/30015
摘要： Disclosed is a Class-AB/B amplifier comprising a first output stage including a first plurality of amplification devices and a second output stage including a second plurality of amplification devices. According to one embodiment, the first output stage operates when the Class-AB/B amplifier is in a quiescent state and the second output stage operates when the Class-AB/B amplifier is in an active state. The Class-AB/B amplifier also comprises a level shifting circuit that adjusts a control voltage of the second output stage, where the level shifting circuit is adapted to activate the second output stage when the Class-AB/B amplifier enters the active state. Embodiments of the Class-AB/B amplifier may include a level shifting circuit that implements either a fixed or signal-dependent level shift, and a quiescent control circuit that substantially eliminates any systematic offset arising from the active feedback circuit inside the replica bias circuit.
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