公开(公告)号：US20090111257A1

公开(公告)日：2009-04-30

申请号：US11924735

申请日：2007-10-26

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/573 ,  H01L27/02 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.

摘要翻译： 提供了反逆向工程技术。 一方面，提供了一种在绝缘层中形成至少一个特征的方法。 该方法包括以下步骤。 离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。 蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同 在植入区域外侧。 空隙填充有至少一种导体材料以在绝缘层中形成特征。

公开(公告)号：US20080258555A1

公开(公告)日：2008-10-23

申请号：US12145622

申请日：2008-06-25

申请人： Rajiv V. Joshi ,  Louis L. Hsu

发明人： Rajiv V. Joshi ,  Louis L. Hsu

IPC分类号： H02J1/10

CPC分类号： G11C11/4074 ,  G06F1/26 ,  G11C5/14 ,  Y10T307/305

摘要： There is provided a circuit for managing a multi-level power supply. The circuit includes a comparator that compares a voltage level (Vs1) of a lower voltage supply bus to a voltage level (Vs2) of a higher voltage supply bus, and a switch that routes current from the lower voltage supply bus to the higher voltage supply bus if Vs2

摘要翻译： 提供了一种用于管理多电平电源的电路。 电路包括比较器，其将较低电压供应总线的电压电平（Vs1）与较高电压电源总线的电压电平（Vs2）进行比较，以及将电流从低电压供应总线传送到较高电压源的开关 总线如果Vs2

公开(公告)号：US07404113B2

公开(公告)日：2008-07-22

申请号：US11031138

申请日：2005-01-07

申请人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

发明人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

IPC分类号： G11C29/00

CPC分类号： G11C29/808

摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

摘要翻译： 提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。 行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 复制逻辑模块被编程为根据可选择的修复字段大小将至少一个故障地址复制到存储在对应于预定数量的存储体的行熔丝阵列中的行熔丝信息中。

公开(公告)号：US07307011B2

公开(公告)日：2007-12-11

申请号：US11129325

申请日：2005-05-16

申请人： George C. Feng ,  Louis L. Hsu ,  Rajiv V. Joshi

发明人： George C. Feng ,  Louis L. Hsu ,  Rajiv V. Joshi

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.

摘要翻译： 一种通过在半导体衬底上形成虚设结构而在电子器件上选择性地形成电介质室的方法（和结构），在虚拟结构上沉积介电层，通过介电层形成通向虚拟结构的开口， 虚拟结构形成电介质室。

公开(公告)号：US07057866B2

公开(公告)日：2006-06-06

申请号：US09929591

申请日：2001-08-14

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Chorng-Lii Hwang ,  Toshiaki K. Kirihata ,  Paul C. Parries

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Chorng-Lii Hwang ,  Toshiaki K. Kirihata ,  Paul C. Parries

IPC分类号： G11C8/00

CPC分类号： G11C5/14 ,  G11C5/147

摘要： An integrated circuit system having a plurality of macros is provided. The integrated circuit system includes an external voltage supply input configured for supplying an external voltage to the integrated circuit; and a plurality of internal voltage supply generators, each of the plurality of internal voltage supply generators being connected to a respective macro of the plurality of macros and configured for receiving the external voltage via the external voltage supply input for generating an internal voltage supply for operating its respective macro. Each of the plurality of internal voltage supply generators includes circuitry for generating the internal voltage supply and circuitry for disconnecting at least a portion of its respective macro. The integrated circuit system can be applied to a semiconductor chip to save active or stand-by power. It can also be used to disconnect a defective portion of the chip and optionally replace it with a non-defective portion of the chip.

公开(公告)号：US06778447B2

公开(公告)日：2004-08-17

申请号：US10062972

申请日：2002-01-31

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Jeremy Stephens ,  Daniel Storaska

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Jeremy Stephens ,  Daniel Storaska

IPC分类号： G11C700

CPC分类号： G11C7/1006 ,  G11C7/1048 ,  G11C7/22 ,  G11C2207/104

摘要： A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths is provided. The data communication system includes a central data path including at least one junction circuit configured for exchanging data signals between the central data path and the plurality of data paths of the at least one data path. A respective one junction circuit of the at least one junction circuit includes circuitry for controlling resetting the respective one junction circuit for preparation of a subsequent data transfer through the respective one junction circuit in accordance with receipt of an input junction monitor signal indicating that data has been transferred to the respective one junction circuit. The data communication system further includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths. The data communication system further includes circuitry for controlling the respective one data path in accordance with receipt of a monitor signal indicating that a data transfer operation has been initiated for transfer of data from the respective one data path. The circuitry for controlling includes circuitry for generating a control signal for controlling resetting of the respective one data path after data is transferred for preparation of a subsequent data transfer operation.

摘要翻译： 提供了具有多个数据路径的宽数据宽度半导体存储器系统的自定时数据通信系统。 该数据通信系统包括中央数据路径，该中央数据路径包括至少一个结电路，该至少一个结电路被配置用于在中央数据路径与至少一条数据路径的多条数据路径之间交换数据信号。 所述至少一个结电路的相应的一个结电路包括用于根据接收到指示数据已经被输入的输入结监视器信号来控制复位相应的一个结电路以准备通过相应的一个结电路的后续数据传输的电路 转移到相应的一个结电路。 数据通信系统还包括被配置用于存储数据的多个数据组，其中多个数据组中相应的数据组连接到多个数据路径中相应的一个数据路径。 数据通信系统还包括用于根据接收到指示已经发起数据传送操作的监视信号来控制相应的一个数据路径的电路，用于从相应的一个数据路径传送数据。 用于控制的电路包括用于产生控制信号的电路，该控制信号用于在传送数据以准备随后的数据传送操作之后控制相应的一个数据路径的复位。

公开(公告)号：US06654277B1

公开(公告)日：2003-11-25

申请号：US10143870

申请日：2002-05-14

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Robert C. Wong

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Robert C. Wong

IPC分类号： G11C1100

CPC分类号： G11C11/412

摘要： A static random access memory (SRAM) with cells in one portion having a higher beta ratio than the remaining cells of the array. In a first portion, cells have a low &bgr; ratio for high performance. A second portion of the array contains SRAM cells with a higher &bgr; ratio that are more stable than the cells in the first portion, but are somewhat slower.

摘要翻译： 静态随机存取存储器（SRAM），其中一部分中的单元具有比阵列的剩余单元更高的β比率。 在第一部分中，对于高性能，细胞具有低β比例。 该阵列的第二部分包含具有比第一部分中的细胞更稳定但具有较慢的β比率的SRAM细胞。

公开(公告)号：US06531911B1

公开(公告)日：2003-03-11

申请号：US09611519

申请日：2000-07-07

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Russell J. Houghton

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Russell J. Houghton

IPC分类号： H01L3500

CPC分类号： G05F3/30 ,  G01K7/015 ,  H01L23/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A combined low-voltage, low-power band-gap reference and temperature sensor circuit is provided for providing a band-gap reference parameter and for sensing the temperature of a chip, such as an eDRAM memory unit or CPU chip, using the band-gap reference parameter. The combined sensor circuit is insensitive to supply voltage and a variation in the chip temperature. The power consumption of both circuits, i.e., the band-gap reference and the temperature sensor circuits, encompassing the combined sensor circuit is less than one &mgr;W. The combined sensor circuit can be used to monitor local or global chip temperature. The result can be used to (1) regulate DRAM array refresh cycle time, e.g., the higher the temperature, the shorter the refresh cycle time, (2) to activate an on-chip or off-chip cooling or heating device to regulate the chip temperature, (3) to adjust internally generated voltage level, and (4) to adjust the CPU (or microprocessor) clock rate, i.e., frequency, so that the chip will not overheat. The combined band-gap reference and temperature sensor circuit of the present invention can be implemented within battery-operated devices having at least one memory unit. The low-power circuits of the sensor circuit extend battery lifetime and data retention time of the cells of the at least one memory unit.

摘要翻译： 提供了组合的低压，低功率带隙参考和温度传感器电路，用于提供带隙参考参数，并且用于使用频带参考参数来感测诸如eDRAM存储器单元或CPU芯片的芯片的温度， 间隙参考参数。 组合的传感器电路对电源电压和芯片温度的变化不敏感。 包含组合传感器电路的两个电路（即带隙基准和温度传感器电路）的功耗小于1μW。 组合传感器电路可用于监测局部或全局芯片温度。 结果可用于（1）调节DRAM阵列刷新周期时间，例如温度越高，刷新周期时间越短，（2）启动片上或片外冷却或加热装置来调节 芯片温度，（3）调节内部产生的电压电平，（4）调整CPU（或微处理器）的时钟频率，即频率，使芯片不会过热。 本发明的组合带隙参考和温度传感器电路可以在具有至少一个存储器单元的电池供电的装置内实现。 传感器电路的低功率电路延长了至少一个存储器单元的单元的电池寿命和数据保持时间。

公开(公告)号：US06507237B2

公开(公告)日：2003-01-14

申请号：US10039874

申请日：2002-01-03

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Russell J. Houghton ,  Wayne F. Ellis ,  Jeffrey H. Dreibelbis

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Russell J. Houghton ,  Wayne F. Ellis ,  Jeffrey H. Dreibelbis

IPC分类号： G05F110

CPC分类号： G05F3/265

摘要： A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e.g., one volt to 1.5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e.g., from 1.5 volts to about 2.5 volts, for operating a boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt. A one-volt negative voltage pump circuit is also included for pumping the voltages of at least one corresponding charge pump circuit, even when an operating voltage of the DC generator system is at or near one-volt. The DC voltage generator system is specifically designed to be implemented within battery-operated devices having at least one memory unit. The low-power consumption feature of the DC voltage generator system extends battery lifetime and data retention time of the cells of the at least one memory unit.

公开(公告)号：US06504204B1

公开(公告)日：2003-01-07

申请号：US09693047

申请日：2000-10-21

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Radens Carl

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Radens Carl

IPC分类号： H01L27108

CPC分类号： G11C11/40603 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4097

摘要： The present invention provides a process integration technique which significantly reduces the array size of dual-port DRAM architecture systems. The array is reduced to a size which is significantly smaller than the array size of prior art DRAM architecture systems by using bitlines formed at half-pitch. The present invention also provides dual-port, open-bitline and folded-bitline DRAM arrays where each DRAM cell in the array has at least two vertically-oriented devices therein.

摘要翻译： 本发明提供了显着降低双端口DRAM架构系统的阵列尺寸的工艺集成技术。 通过使用以半间距形成的位线，将阵列减小到比现有技术DRAM架构系统的阵列大小明显更小的尺寸。 本发明还提供双端口，开放位线和折叠位线DRAM阵列，其中阵列中的每个DRAM单元在其中具有至少两个垂直取向的器件。