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    PHYSICAL LAYER SYNCHRONIZATION
    32.
    发明申请
    PHYSICAL LAYER SYNCHRONIZATION 有权

    公开(公告)号：US20240372691A1

    公开(公告)日：2024-11-07

    申请号：US18367383

    申请日：2023-09-12

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Maciek Machnikowski

    IPC: H04L7/00

    Abstract: A system includes a device including a transmitter associated with a link coupled to the device. The device is to receive from an application layer of the device, a first bitstream for transmission. The device is to encode the first bitstream into one or more blocks and transmit the one or more data blocks via the link. The device is also to receive a second bitstream to be transmitted. The device is to encode the second bitstream into a control block and transmit the control block via the link. The control block includes a first portion of bits corresponding to a header indicating the control block includes the second bitstream and a second portion of bits including the second bitstream.

    Application accelerator
    33.
    发明公开
    Application accelerator 审中-公开

    公开(公告)号：US20240333915A1

    公开(公告)日：2024-10-03

    申请号：US18738013

    申请日：2024-06-09

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Dotan David Levi ,  Assaf Weissman ,  Kobi Pines ,  Noam Bloch ,  Erez Yaacov ,  Ariel Naftali Cohen

    IPC: H04N19/105 ,  H04N19/139 ,  H04N19/147 ,  H04N19/176

    CPC classification number: H04N19/105 ,  H04N19/139 ,  H04N19/176 ,  H04N19/147

    Abstract: A system for video encoding includes an acceleration device, to select from a video stream a target video frame and one or more reference frames. The target and reference frames are divided into respective first pluralities of first blocks of a first size and into respective second pluralities of second blocks of a second size, larger than the first size. At least a first map and a second map are computed, including respective motion vectors between each first block in the target video frame and corresponding first blocks in the reference frames, and between each second block in the target video frame and corresponding second blocks in the one or more reference frames. A control unit encodes the target video frame based on at least one of the reference frames by selecting motion vectors from among the motion vectors in the first and second maps.

    SYNTONIZATION THROUGH PHYSICAL LAYER OF INTERCONNECTS
    36.
    发明公开
    SYNTONIZATION THROUGH PHYSICAL LAYER OF INTERCONNECTS 审中-公开

    公开(公告)号：US20240031124A1

    公开(公告)日：2024-01-25

    申请号：US17868841

    申请日：2022-07-20

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich

    IPC: H04L7/027 ,  H04L12/40

    CPC classification number: H04L7/027 ,  H04L12/40

    Abstract: In one embodiment, a clock syntonization system includes a first compute node including a first physical hardware clock to operate at a first clock frequency, a second compute node, and an interconnect data bus to transfer data from the first compute node at a data rate indicative of the first clock frequency of the first physical hardware clock, and wherein the second compute node includes clock synchronization circuitry to derive a second clock frequency from the data rate of the transferred data, and provide a clock signal at the derived second clock frequency.

    Scalable Boundary Clock
    38.
    发明公开
    Scalable Boundary Clock 审中-公开

    公开(公告)号：US20230367358A1

    公开(公告)日：2023-11-16

    申请号：US17867779

    申请日：2022-07-19

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Ariel Almog ,  Bar Shapira

    IPC: G06F1/12 ,  G06F1/10 ,  G06F1/06

    CPC classification number: G06F1/12 ,  G06F1/10 ,  G06F1/06

    Abstract: In one embodiment, a synchronized communication system includes a first network device and a second network device, wherein the first network device includes a first physical hardware clock, and is configured to recover a reference clock time from packets received from a remote clock, find a clock differential between a clock time output by the first physical hardware clock and the recovered reference clock time, provide a control signal to the second network device responsively to the clock differential, and the second network device includes a second physical hardware clock, and is configured to adjust a clock time output by the second physical hardware clock responsively to the control signal.

    Regrouping of video data in host memory
    40.
    发明授权
    Regrouping of video data in host memory 有权

    公开(公告)号：US11700414B2

    公开(公告)日：2023-07-11

    申请号：US17542426

    申请日：2021-12-05

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Dotan David Levi ,  Michael Kagan

    IPC: H04N21/00 ,  H04N21/426 ,  G06T1/60

    CPC classification number: H04N21/42607 ,  G06T1/60 ,  H04N21/42653

    Abstract: Apparatus for data communications includes a host interface, which is configured to be connected to a bus of a host computer having a processor and a memory. Processing circuitry, which is coupled to the host interface, is configured to receive video data with respect to a sequence of pixels, the video data including data words of more than eight bits per pixel for at least one pixel component of the pixels, and to write the video data, via the host interface, to at least one buffer in the memory while justifying the video data in the memory so that the successive pixels in the sequence are byte-aligned in the at least one buffer.

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