公开(公告)号：US11323372B2

公开(公告)日：2022-05-03

申请号：US16853783

申请日：2020-04-21

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Avi Urman ,  Lior Narkis ,  Ariel Shahar

IPC: H04L45/7453 ,  H04L47/22

Abstract: In one embodiment, a network device includes an interface configured to receive a data packet including a header section, at least one parser to parse the data of the header section yielding a first header portion and a second header portion, a packet processing engine to fetch a first match-and-action table, match a first index having a corresponding first steering action entry in the first match-and-action table responsively to the first header portion, compute a cumulative lookup value based on the first header portion and the second header portion responsively to the first steering action entry, fetch a second match-and-action table responsively to the first steering action entry, match a second index having a corresponding second steering action entry in the second match-and-action table responsively to the cumulative lookup value, and steering the packet responsively to the second steering action entry.

公开(公告)号：US20220116473A1

公开(公告)日：2022-04-14

申请号：US17067690

申请日：2020-10-11

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Daniel Marcovitch ,  Lior Narkis ,  Avi Urman

IPC: H04L29/08

Abstract: A Network-Connected Device (NCD) includes a network interface, a host interface, an NCD memory and an NCD processor. The network interface is configured for communicating over a network. The host interface is configured for communicating with a host. The NCD memory is configured to buffer packet information that originates from the host and pertains to a packet to be transmitted to the network at a specified transmission time. The NCD processor is configured to process the buffered packet information before the specified transmission time, and to transmit the packet to the network at the specified time. Processing of the packet information and transmission of the packet are decoupled from buffering of the packet information.

公开(公告)号：US20210243121A1

公开(公告)日：2021-08-05

申请号：US16780940

申请日：2020-02-04

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Avi Urman ,  Lior Narkis ,  Noam Bloch

IPC: H04L12/741 ,  G06F13/42 ,  H04L29/06

Abstract: A communication apparatus includes a host interface, connected to a peripheral component bus so as to communicate with a CPU and a memory of a host computer. A network interface is connected to a network. Packet processing circuitry is configured to receive from a first interface a data packet including a set of one or more headers that include header fields having respective values, to identify, responsively to at least one of the header fields, a corresponding entry in a header modification table that specifies a header modification operation, to modify the set of headers in accordance with the header modification operation, to check whether the entry specifies an additional header modification operation, to output the modified set of headers if the entry does not specify an additional header modification operation, and, if the entry specifies an additional header modification operation, to feed-back the modified set of headers.

公开(公告)号：US10572400B2

公开(公告)日：2020-02-25

申请号：US15623426

申请日：2017-06-15

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Finkelstein ,  Lior Narkis ,  Dror Bohrer ,  Roee Moyal

IPC: G06F13/16 ,  G06F13/36 ,  H04L12/801

Abstract: A packet processing device CPU, including multiple processing cores. A NIC, which is coupled to the CPU, includes at least one network port, receives a flow of incoming data packets in a sequential order from a packet communication network, and receive logic, which delivers the incoming data packets in the flow to a designated group of the cores for processing by the cores in the group, while distributing the incoming data packets to the cores in alternation among the cores in the group. In response to the incoming data packets, the cores in the group generate corresponding outgoing data packets and queue the outgoing data packets for transmission by the NIC in the sequential order of the incoming data packets. Transmit logic in the NIC transmits the outgoing data packets to the network in the sequential order via the at least one network port.

公开(公告)号：US20190089641A1

公开(公告)日：2019-03-21

申请号：US15996548

申请日：2018-06-04

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Guy Shattah ,  Ron Efraim ,  Lior Narkis

IPC: H04L12/851 ,  H04L12/801 ,  H04L12/931 ,  H04L29/06

Abstract: A mechanism is provided for partial offload of connection tracking from a host processor to a network interface device. Software running in the host processor is used for connection establishment. After a connection has been established the software initializes and transfers flow-control to the network interface device. Thereafter, the network interface device continues transferring packets to the destination, while the software in the host processor monitors the flow. If the connection has been terminated or has expired flow control reverts to the software. Modes of operation are provided for network interface devices with and without a specific connection-tracking module.

公开(公告)号：US20180365176A1

公开(公告)日：2018-12-20

申请号：US15623426

申请日：2017-06-15

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Finkelstein ,  Lior Narkis ,  Dror Bohrer ,  Roee Moyal

IPC: G06F13/16 ,  H04L12/801 ,  G06F13/36

CPC classification number: G06F13/1642 ,  G06F13/36 ,  H04L47/34

Abstract: A packet processing device CPU, including multiple processing cores. A NIC, which is coupled to the CPU, includes at least one network port, receives a flow of incoming data packets in a sequential order from a packet communication network, and receive logic, which delivers the incoming data packets in the flow to a designated group of the cores for processing by the cores in the group, while distributing the incoming data packets to the cores in alternation among the cores in the group. In response to the incoming data packets, the cores in the group generate corresponding outgoing data packets and queue the outgoing data packets for transmission by the NIC in the sequential order of the incoming data packets. Transmit logic in the NIC transmits the outgoing data packets to the network in the sequential order via the at least one network port.

公开(公告)号：US12218860B2

公开(公告)日：2025-02-04

申请号：US16932765

申请日：2020-07-19

Applicant: Mellanox Technologies, Ltd.

Inventor： Gal Yefet ,  Avi Urman ,  Gil Kremer ,  Lior Narkis ,  Boris Pismenny

IPC: H04L49/90 ,  G06F9/54 ,  H04L47/2441 ,  H04L69/22

Abstract: A network node includes a network adapter and a host. The network adapter is coupled to a communication network. The host includes a processor running a client process and a communication stack, and is configured to receive packets from the communication network, and classify the received packets into respective flows that are associated with respective chunks in a receive buffer, to distribute payloads of the received packets among the chunks so that payloads of packets classified to a given flow are stored in a given chunk assigned to the given flow, and to notify the communication stack of the payloads in the given chunk, for transferring the payloads in the given chunk to the client process.

公开(公告)号：US20240193106A1

公开(公告)日：2024-06-13

申请号：US18444804

申请日：2024-02-19

Applicant: Mellanox Technologies, Ltd.

Inventor： Idan Burstein ,  Dotan David Levi ,  Ariel Shahar ,  Lior Narkis ,  Igor Voks ,  Noam Bloch ,  Shay Aisman

IPC: G06F13/16 ,  G06F9/455 ,  G06F9/46 ,  G06F12/1045 ,  G06F13/38 ,  G06F13/42 ,  G06F15/173

CPC classification number: G06F13/1668 ,  G06F9/45558 ,  G06F9/466 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/387 ,  G06F13/4221 ,  G06F15/17331 ,  G06F2009/45579

Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

公开(公告)号：US11940933B2

公开(公告)日：2024-03-26

申请号：US17189303

申请日：2021-03-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Burstein ,  Dotan David Levi ,  Ariel Shahar ,  Lior Narkis ,  Igor Voks ,  Noam Bloch ,  Shay Aisman

IPC: G06F13/16 ,  G06F9/455 ,  G06F9/46 ,  G06F12/1045 ,  G06F13/38 ,  G06F13/42 ,  G06F15/173

CPC classification number: G06F13/1668 ,  G06F9/45558 ,  G06F9/466 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/387 ,  G06F13/4221 ,  G06F15/17331 ,  G06F2009/45579

Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

公开(公告)号：US20220407824A1

公开(公告)日：2022-12-22

申请号：US17899652

申请日：2022-08-31

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Yefet ,  Daniel Marcovitch ,  Roee Moyal ,  Ariel Shahar ,  Gil Bloch ,  Lior Narkis

IPC: H04L49/9005 ,  H04L49/901 ,  H04L41/0604

Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface connects to a communication network for communicating with remote targets. The host interface connects to a host that accesses a Multi-Channel Send Queue (MCSQ) storing Work Requests (WRs) originating from client processes running on the host. The processing circuitry is configured to retrieve WRs from the MCSQ and distribute the WRs among multiple Send Queues (SQs) accessible by the processing circuitry, and retrieve WRs from the multiple NSQs and execute data transmission operations specified in the WRs retrieved from the multiple NSQs.