公开(公告)号：US20200084150A1

公开(公告)日：2020-03-12

申请号：US16559640

申请日：2019-09-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Idan Burstein ,  Noam Bloch ,  Roee Moyal ,  Ariel Shahar ,  Yamin Friedman ,  Yuval Shpigelman

IPC: H04L12/801 ,  H04L12/927 ,  H04L12/841 ,  H04L12/863 ,  H04L29/08

Abstract: A network adapter includes circuitry and one or more ports. The ports connect to a communication network including multiple network elements. The circuitry accesses outbound messages that are pending to be sent over the communication network to multiple remote nodes via the ports. At least some of the outbound messages request the remote nodes to send respective amounts of data back to the network adapter. Based on the amounts of data requested by the outbound messages, the circuitry forecasts a bandwidth of inbound response traffic, which is expected to traverse a selected network element in response to the outbound messages toward the network adapter, determines a schedule for transmitting the outbound messages to the remote nodes so that the forecasted bandwidth meets a bandwidth supported by the selected network element, and transmits the outbound messages to the remote nodes in accordance with the determined schedule.

公开(公告)号：US20250030649A1

公开(公告)日：2025-01-23

申请号：US18224258

申请日：2023-07-20

Applicant: Mellanox Technologies, Ltd.

Inventor： Ortal Ben Moshe ,  Roee Moyal ,  Shay Aisman ,  Gil Bloch ,  Ariel Shahar ,  Roman Nudelman ,  Gil Kremer ,  Yossef Itigin ,  Lior Narkis

IPC: H04L49/9057

Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and packet processing circuitry operatively coupled to the network interface. The packet processing circuitry is configured to receive, via the network interface, a plurality of data packets associated with a message; determine, for each data packet, at least one corresponding reserved stride in a strided buffer; store each data packet in the at least one corresponding reserved stride; process the strided buffer upon storing the plurality of data packets in a corresponding plurality of reserved strides; and generate a completion notification indicating that the plurality of data packets in the strided buffer has been processed.

公开(公告)号：US12132665B2

公开(公告)日：2024-10-29

申请号：US17990768

申请日：2022-11-21

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Yamin Friedman ,  Idan Burstein ,  Ariel Shahar ,  Roee Moyal ,  Gil Kremer

IPC: H04L47/62 ,  H04L47/6275 ,  H04L49/90

CPC classification number: H04L47/624 ,  H04L47/6275 ,  H04L49/9036

Abstract: An apparatus includes a memory and control circuitry. The control circuitry is configured to receive packets, which are en-route to undergo transport-layer processing in a network device in accordance with a transport protocol that requires arrival of the packets in a sequential order, to detect that one or more of the packets deviate from the sequential order, to buffer the one or more deviating packets in the memory, and, using the memory, to reorder the packets and provide the packets in the sequential order to the network device.

公开(公告)号：US12101239B2

公开(公告)日：2024-09-24

申请号：US18106953

申请日：2023-02-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Roee Moyal

IPC: H04L12/00 ,  H04J3/06 ,  H04L43/0888 ,  H04L47/22 ,  H04L47/25 ,  H04L47/263

CPC classification number: H04L43/0888 ,  H04J3/0652 ,  H04J3/0667 ,  H04L47/225 ,  H04L47/25 ,  H04L47/263

Abstract: A system includes a device coupled to a processing device. The processing device is to receive a request to execute a plurality of workloads, the request comprising a rate to execute each workload of the plurality of workloads and a parameter value indicating an execution offset. The processing device is further to determine a sequence for executing the plurality of workloads based on receiving the rate and the parameter value, where the sequence is to execute each workload at the respective rate and each workload of the plurality of workloads is executed at a different time based on the parameter value. The processing device is to execute the plurality of workloads in accordance with the sequence upon determining the sequence to execute the plurality of workloads.

公开(公告)号：US20240080379A1

公开(公告)日：2024-03-07

申请号：US17902150

申请日：2022-09-02

Applicant: Mellanox Technologies, Ltd.

Inventor： Yamin Friedman ,  Ariel Shahar ,  Idan Borshteen ,  Roee Moyal

IPC: H04L69/22 ,  G06F13/28 ,  G06F15/167 ,  H04L49/90

CPC classification number: H04L69/22 ,  G06F13/28 ,  G06F15/167 ,  H04L49/90

Abstract: Technologies for payload direct memory storing (PDMS) for out-of-order delivery of packets in remote direct memory access (RDMA) are described. A responder device includes an RDMA transport layer that can receive packets out of order and allow direct data placement of packet data in order. The responder device receives a first packet with a first packet number and first location information. The responder device stores first packet data to a first location according to the first location information. The responder device also receives a second packet and stores second packet data to a second location according to the second location information. A second packet number indicates that the first packet is received out of order. The first and second packet data are stored in order. The responder device can provide an indication that a message has arrived in response to determining that all packets of the message have arrived.

公开(公告)号：US11909628B1

公开(公告)日：2024-02-20

申请号：US17901671

申请日：2022-09-01

Applicant: Mellanox Technologies, Ltd.

Inventor： Yamin Friedman ,  Idan Borshteen ,  Roee Moyal ,  Yuval Shpigelman

IPC: H04L43/0864 ,  H04L45/24 ,  H04L45/12 ,  H04L47/52

CPC classification number: H04L45/124 ,  H04L43/0864 ,  H04L45/24 ,  H04L47/52

Abstract: Technologies for spreading a single transport flow across multiple network paths in remote direct memory access (RDMA) over converged Ethernet (RoCE) and InfiniBand are described. A network interface controller receives a first packet and a second packet of a transport flow directed to a second node. The network interface controller assigns a first network routing identifier to the first packet and a second network routing identifier to the second packet, the first network routing identifier corresponding to a first network path between the first and second nodes, the second network routing identifier corresponding to a second network path between the first node and the second node. The network interface controller schedules a first packet of the transport flow to be sent via the first network path and a second packet of the transport flow to be sent via the second network path.

公开(公告)号：US20230362084A1

公开(公告)日：2023-11-09

申请号：US18106933

申请日：2023-02-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Alex Vainman ,  Roee Moyal

IPC: H04L43/0888

CPC classification number: H04L43/0888

Abstract: A system includes a device configured to execute workloads coupled to a processing device. The processing device is to receive a request to execute one or more workloads, the request comprising two or more numbers corresponding to a rational value associated with a rate to execute the one or more workloads. The processing device is further to determine the rate to execute the one or more workloads responsive to receiving the two or more numbers corresponding to the rational values. The processing device is to execute the one or more workloads at the determined rate.

公开(公告)号：US20220217101A1

公开(公告)日：2022-07-07

申请号：US17142366

申请日：2021-01-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Yefet ,  Daniel Marcovitch ,  Roee Moyal ,  Ariel Shahar ,  Gil Bloch ,  Lior Narkis

IPC: H04L12/879 ,  H04L12/861 ,  H04L12/937 ,  H04L12/24

Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface connects to a communication network for communicating with remote targets. The host interface connects to a host that accesses a Multi-Channel Send Queue (MCSQ) storing Work Requests (WRs) originating from client processes running on the host. The processing circuitry is configured to retrieve WRs from the MCSQ and distribute the WRs among multiple Send Queues (SQs) accessible by the processing circuitry.

公开(公告)号：US11296988B2

公开(公告)日：2022-04-05

申请号：US16986428

申请日：2020-08-06

Applicant: Mellanox Technologies, Ltd.

Inventor： Yuval Shpigelman ,  Idan Burstein ,  Noam Bloch ,  Reut Zuck ,  Roee Moyal

IPC: H04L1/00 ,  H04L47/12 ,  H04L47/2441 ,  H04L69/22 ,  H04L67/104 ,  H04L47/25

Abstract: A network adapter includes a receive (Rx) pipeline, a transmit (Tx) pipeline and congestion management circuitry. The Rx pipeline is configured to receive packets sent over a network by a peer network adapter, and to process the received packets. The Tx pipeline is configured to transmit packets to the peer network adapter over the network. The congestion management circuitry is configured to receive, from the Tx pipeline and from the Rx pipeline, Congestion-Control (CC) events derived from at least some of the packets exchanged with the peer network adapter, to exchange user-programmable congestion control packets with the peer network adapter, and to mitigate a congestion affecting one or more of the packets responsively to the CC events and the user-programmable congestion control packets.

公开(公告)号：US11218413B2

公开(公告)日：2022-01-04

申请号：US16683302

申请日：2019-11-14

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Yuval Shpigelman ,  Roee Moyal ,  Shahrazad Hleihel ,  Kobi Pines

IPC: H04L1/00 ,  H04L12/825 ,  H04L12/841 ,  H04L12/823 ,  H04L12/861

Abstract: A network adapter includes a receive (RX) pipeline, a transmit (TX) pipeline, hardware-implemented congestion-control circuitry, and a congestion-control processor. The RX pipeline is configured to receive packets from a network and process the received packets. The TX pipeline is configured to transmit packets to the network. The hardware-implemented congestion-control circuitry is configured to receive, from the TX pipeline and from the RX pipeline, Congestion-Control (CC) events derived from at least some of the packets transmitted to the network and from at least some of the packets received from the network, and to pre-process the CC events. The congestion-control processor is configured to receive the pre-processed CC events from the congestion-control circuitry, and to throttle a transmission rate of the packets transmitted to the network by the TX pipeline responsively to the pre-processed CC events.