公开(公告)号：US20200092229A1

公开(公告)日：2020-03-19

申请号：US16693302

申请日：2019-11-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Avi Urman

IPC: H04L12/939 ,  H04L12/861 ,  H04L12/879 ,  H04L29/06 ,  H04W28/04

Abstract: Communication apparatus includes a host interface and a network interface, which receives from a packet communication network at least one packet stream including a sequence of data packets, which include headers containing respective sequence numbers and data payloads containing slices of the data segment having a predefined, fixed size per slice. Packet processing circuitry is configured to receive the data packets from the network interface, and to map the data payloads of the data packets in the at least one packet stream, using a linear mapping of the sequence numbers, to respective addresses in the buffer.

公开(公告)号：US20250023705A1

公开(公告)日：2025-01-16

申请号：US18219895

申请日：2023-07-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Thomas Kernen

IPC: H04L7/00

Abstract: A network device includes control logic coupled to a receiver. The control logic detects an synchronization packet received via the receiver from a second network device over a network that is precision time protocol unaware. The control logic determines that a portion of the synchronization packet is asserted, indicating that the synchronization packet has incurred congestion traversing the network. The control logic adjusts, based on an assertion of the portion, a weight applied to timestamps associated with sending and receiving the synchronization packet in performing clock synchronization with the second network device.

公开(公告)号：US20240244225A1

公开(公告)日：2024-07-18

申请号：US18096428

申请日：2023-01-12

Applicant: Mellanox Technologies, Ltd.

Inventor： Eshed Ram ,  Dotan David Levi ,  Assaf Hallak ,  Shie Mannor ,  Gal Chechik ,  Eyal Frishman ,  Ohad Markus ,  Dror Porat ,  Assaf Weissman

IPC: H04N19/147 ,  H04N19/124 ,  H04N19/172

CPC classification number: H04N19/147 ,  H04N19/124 ,  H04N19/172

Abstract: A system includes a processing device to receive video content, metadata related to the video content, and a target bit rate for encoding the video content. The processing device further detects a content type of the video content based on the metadata and encodes hardware to perform frame encoding on the video content. The system further includes a controller coupled between the processing device and the encoding hardware. The controller is programmed with machine instructions to generate first QP values on a per-frame basis using a frame machine learning model with a first plurality of weights. The first plurality of weights depends at least in part on the content type and the target bit rate. The controller further provides the first QP values to the encoding hardware for rate control of the frame encoding.

公开(公告)号：US20240231984A9

公开(公告)日：2024-07-11

申请号：US18074751

申请日：2022-12-05

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Shay Aisman ,  Ariel Almog ,  Ran Avraham Koren

IPC: G06F11/07

CPC classification number: G06F11/0757 ,  G06F11/0736

Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.

公开(公告)号：US12028661B2

公开(公告)日：2024-07-02

申请号：US17869932

申请日：2022-07-21

Applicant: Mellanox Technologies, Ltd.

Inventor： Ioannis (Giannis) Patronas ,  Dotan David Levi ,  Wojciech Wasko ,  Paraskevas Bakopoulos ,  Dimitrios Syrivelis ,  Elad Mentovich

IPC: H04B10/2575 ,  H04B10/40 ,  H04B10/50 ,  H04B10/60 ,  H04Q11/00

CPC classification number: H04Q11/0005 ,  H04B10/25753 ,  H04B10/40 ,  H04B10/50 ,  H04B10/60 ,  H04Q2011/0045 ,  H04Q2011/005

Abstract: Network devices and associated methods are provided for synchronization in an optically switched network. The network device includes one or more ports in communication with a plurality of devices via an optical switch. The one or more ports receive a master clock signal having a first frequency from a first device of the plurality of devices. The network device includes a local clock in communication with the one or more ports and operating at a second frequency. The network device includes a synchronization manager in communication with the one or more ports and the local clock and configured to be enabled and disabled. When the synchronization manager is enabled, it receives the master clock signal via the one or more ports and transmits an instruction to the local clock to operate at the first frequency.

公开(公告)号：US12028155B2

公开(公告)日：2024-07-02

申请号：US17534776

申请日：2021-11-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Bar Shapira ,  Ariel Almog ,  Dotan David Levi ,  Natan Manevich ,  Thomas Kernen ,  Liron Mula

IPC: H04J3/06

CPC classification number: H04J3/0638

Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.

公开(公告)号：US11979340B2

公开(公告)日：2024-05-07

申请号：US17824954

申请日：2022-05-26

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Boris Pismenny ,  Dotan David Levi ,  Gal Yefet

IPC: H04L65/61 ,  H04L49/552 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9057 ,  H04L65/65 ,  H04W28/04

CPC classification number: H04L49/552 ,  H04L49/901 ,  H04L49/9057 ,  H04L49/9068 ,  H04L65/61 ,  H04L65/65 ,  H04W28/04

Abstract: A method for communication includes mapping transport sequence numbers in headers of data packets received from a network to respective buffers in a memory of a host computer. At least a part of the data from payloads of the received data packets is written directly to the respective buffers.

公开(公告)号：US20240146431A1

公开(公告)日：2024-05-02

申请号：US17973575

申请日：2022-10-26

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Avi Urman ,  Natan Manevich

IPC: H04J3/06

CPC classification number: H04J3/0638

Abstract: In one embodiment, a system includes a network interface controller including a device interface to connect to a processing device and receive a time synchronization marker message from an application running on the processing device, a network interface to send packets over a network, and packet processing circuitry to process the time synchronization marker message for sending via the network interface over the network to a slave clock device, generate a time synchronization follow-up message including a timestamp indicative of when the synchronization marker message egressed the network interface, and process the time synchronization follow-up message for sending via the network interface over the network to the slave clock device.

公开(公告)号：US20240097876A1

公开(公告)日：2024-03-21

申请号：US18523991

申请日：2023-11-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Ariel Shahar ,  Shahaf Shuler ,  Ariel Almog ,  Eitan Hirshberg ,  Natan Manevich

IPC: H04L7/00

CPC classification number: H04L7/0091

Abstract: A communication system includes at least one send queue, containing send queue entries pointing to packets to be transmitted over a network by packet sending circuitry. A clock work queue contains clock queue entries to synchronize sending times of the packets pointed to by the send queue entries. At least one arming queue contains arming queue entries to arm the clock work queue at selected time intervals.

公开(公告)号：US20240014916A1

公开(公告)日：2024-01-11

申请号：US17858236

申请日：2022-07-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Thomas Kernen ,  Dotan David Levi ,  Bar Or Shapira ,  Georgi Mihaylov Chalakov ,  Aviad Itzhak Raveh

IPC: H04J3/06

CPC classification number: H04J3/0697

Abstract: System, methods, and devices for sharing time information between machines are provided. In one example, a system includes a Precision Time Protocol (PTP) Hardware Clock (PHC) and an application. The application receives time information from the PHC along with contextual metadata associated with the time information, analyzes the contextual metadata associated with the time information, and determines a context in which the PHC is disciplined. The context in which the PHC is disciplined may control a manner in which the application uses the time information.