公开(公告)号：US12189974B2

公开(公告)日：2025-01-07

申请号：US17345267

申请日：2021-06-11

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Todd J. Plum ,  Scott D. Van De Graaff ,  Scott E. Schaefer ,  Mark D. Ingram

IPC: G06F3/06 ,  G06F1/06

Abstract: Methods, systems, and devices for operational monitoring for memory devices are described. Some memory devices may degrade over time, and this degradation may include or refer to a reduction of an ability of the memory device to reliably store, read, process, or communicate information, among other degradation. In accordance with examples as disclosed herein, a memory device may include components configured for monitoring health or life expectancy or both of the memory device, such as components internal to the memory device that identify and store various indications of a duration of operating a memory device. An operational duration stored at the memory device may be used in various operations, such as calculations or comparisons, to evaluate health or life expectancy of the memory device, which may include or be supported by various signaling with a host device.

公开(公告)号：US20240412801A1

公开(公告)日：2024-12-12

申请号：US18742749

申请日：2024-06-13

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G11C29/42 ,  G11C8/18 ,  G11C29/12 ,  G11C29/14

Abstract: Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may fail to receive or decode (e.g., successfully receive or successfully decode) an access command transmitted to the memory device via a bus. The bus may enter or remain in an idle state which may cause indeterminate signals to develop on the idle bus. A host device may obtain the indeterminate signals from the idle bus and determine that the indeterminate signals include an error based on a signal that develops on a control line of the idle bus. The signal may be associated with a control signal that indicates errors in a data signal when the control signal has a first voltage, and the control line may be configured to have the first voltage when the bus is idle.

公开(公告)号：US20240361950A1

公开(公告)日：2024-10-31

申请号：US18660070

申请日：2024-05-09

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Steffen Buch ,  Lance W. Dover

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0623 ,  G06F3/0679

Abstract: Methods, systems, and devices for host verification for a memory device are described. A memory device may receive a first value from a host device that is associated with an identification of the host device after an event. The memory device may transmit a second value to the host device that is based on the first value and comprises a random set of bits. The memory device may receive from the host device data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device. The memory device may also enable a functionality of the memory device based on the encrypted third value.

公开(公告)号：US12046316B2

公开(公告)日：2024-07-23

申请号：US17502982

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G11C8/18 ,  G11C29/12 ,  G11C29/14 ,  G11C29/42

CPC classification number: G11C29/42 ,  G11C8/18 ,  G11C29/12005 ,  G11C29/14 ,  G11C2029/1208

Abstract: Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may fail to receive or decode (e.g., successfully receive or successfully decode) an access command transmitted to the memory device via a bus. The bus may enter or remain in an idle state which may cause indeterminate signals to develop on the idle bus. A host device may obtain the indeterminate signals from the idle bus and determine that the indeterminate signals include an error based on a signal that develops on a control line of the idle bus. The signal may be associated with a control signal that indicates errors in a data signal when the control signal has a first voltage, and the control line may be configured to have the first voltage when the bus is idle.

公开(公告)号：US12009835B2

公开(公告)日：2024-06-11

申请号：US17814402

申请日：2022-07-22

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Melissa I. Uribe

IPC: H03M13/11 ,  G11C8/06 ,  H03M13/09

CPC classification number: H03M13/1174 ,  G11C8/06 ,  H03M13/098

Abstract: Implementations described herein relate to command address fault detection. A memory device may receive, from a host device via a command address (CA) bus, a plurality of bits associated with a command signal or an address signal. The CA bus may be configured for communicating command signals and address signals between the memory device and the host device. The memory device may generate one or more parity bits based on the plurality of bits. The one or more parity bits may be generated using a parity generation process that is common to the memory device and the host device. The memory device may transmit, to the host device, the one or more parity bits.

公开(公告)号：US11977772B2

公开(公告)日：2024-05-07

申请号：US17464333

申请日：2021-09-01

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Todd Jackson Plum ,  Scott D. Van De Graaff ,  Scott E. Schaefer ,  Mark D. Ingram

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679

Abstract: Methods, systems, and devices for temperature monitoring for memory devices are described for monitoring one or more temperature ranges experienced by a memory device. The memory device may include monitoring circuitry or logic that may identify one or more durations of operating the memory device within the one or more temperature ranges. The memory device may store an indication of the one or more durations, or an indication of information associated with the one or more durations. The indication may be accessed a host device associated with the memory device or may be transmitted by the memory device to the host device. The host device may use information included in the indication to perform an operation associated with the memory device.

公开(公告)号：US20230394143A1

公开(公告)日：2023-12-07

申请号：US18104079

申请日：2023-01-31

Applicant: Micron Technology, Inc

Inventor： Aaron P. Boehm ,  David Hulton ,  Jeremy Chritz ,  Tamara Schmitz ,  Max S. Vohra

IPC: G06F21/55 ,  G06F21/57 ,  G06F21/79

CPC classification number: G06F21/556 ,  G06F21/575 ,  G06F21/79

Abstract: Methods, systems, and devices for protective actions for a memory device based on detecting an attack are described. In some systems, a memory device may detect whether a fault is injected into the memory device. The memory device may apply a delay during boot up if a fault is detected. To ensure the delay is applied, the memory device may default to applying the delay and may remove an indication to apply the delay if a fault is not detected. Additionally or alternatively, the memory device may erase information from non-volatile memory during boot up, for example, if a fault is detected. The memory device may be configured to ensure at least a specific portion of memory resources (e.g., resources configured to store sensitive information) is erased during boot up. In some examples, the memory device may store data using a stream cipher to improve security of the data.

公开(公告)号：US11789818B2

公开(公告)日：2023-10-17

申请号：US17690772

申请日：2022-03-09

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F11/10 ,  H03M13/29

CPC classification number: G06F11/1076 ,  H03M13/2906

Abstract: Methods, systems, and devices for coordinated error correction are described. A memory device indicates, to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. Based on a result of the comparison, an indication of whether the compared error correction codes match is provided to the external device. The external device uses the indication to detect errors in the received version of the data, to manage data storage in the memory device, or both.

公开(公告)号：US11789647B2

公开(公告)日：2023-10-17

申请号：US17098096

申请日：2020-11-13

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0671 ,  G06F2212/7209

Abstract: Methods, systems, and devices for address verification for a memory device are described. When a memory device receives a write command, the memory device may store, in association with the data written, an indication of a write address associated with the write command. When the memory device receives a read command, the memory device may retrieve data and a previously stored write address associated with the retrieved data, and the memory device may verify a read address associated with the read command against the previously stored write address associated with retrieved data. Thus, for example, the memory device may verify whether data read from the memory array based on an address associated with a read command is data that, when previously written to the memory array, was written in response to a write command associated with a matching address.

公开(公告)号：US11762585B2

公开(公告)日：2023-09-19

申请号：US17180503

申请日：2021-02-19

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G06F3/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/22

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0673 ,  G11C11/221 ,  G11C11/4087 ,  G11C11/4091

Abstract: Methods, systems, and devices related to operating a memory array are described. A system may include a memory device and a host device. A memory device may indicate information about a temperature of the memory device, which may include sending an indication to the host device after receiving a signal that initializes the operation of the memory device or storing an indication, for example in a register, about the temperature of the memory device. The information may include an indication that a temperature of the memory device or a rate of change of the temperature of the memory device has satisfied a threshold. Operation of the memory device, or the host device, or both may be modified based on the information about the temperature of the memory device. Operational modifications may include delaying a sending or processing of memory commands until the threshold is satisfied.