公开(公告)号：US10777561B2

公开(公告)日：2020-09-15

申请号：US16258987

申请日：2019-01-28

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Sanjeev Sapra ,  Masihhur R. Laskar ,  Darwin Franseda Fan ,  Jerome A. Imonigie

IPC: H01L27/108

Abstract: Methods, apparatuses, and systems related to reduction of tapering on a sidewall of an opening are described. An example method includes forming a silicate material comprising a gradient borophosphosilicate glass (BPSG) stack on a semiconductor structure. The example method further includes etching a portion of the silicate material to form an opening within the silicate material having sidewalls, wherein the gradient BSPG stack comprises varying concentrations of boron and phosphorous to reduce tapering of the sidewalls in response to the etching.

公开(公告)号：US20200266280A1

公开(公告)日：2020-08-20

申请号：US16799517

申请日：2020-02-24

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Darwin Franseda Fan

IPC: H01L29/49 ,  H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11556

Abstract: Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.

公开(公告)号：US20160133752A1

公开(公告)日：2016-05-12

申请号：US14987147

申请日：2016-01-04

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Darwin Franseda Fan ,  Fatma Arzum Simsek-Ege ,  James Brighten ,  Aurelio Giancarlo Mauri ,  Srikant Jayanti

IPC: H01L29/788 ,  H01L27/115

CPC classification number: H01L29/7887 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7881 ,  H01L29/7889

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

公开(公告)号：US09230986B2

公开(公告)日：2016-01-05

申请号：US14610755

申请日：2015-01-30

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Darwin Franseda Fan ,  Fatma Arzum Simsek-Ege ,  James Brighten ,  Aurelio Giancarlo Mauri ,  Srikant Jayanti

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/7887 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7881 ,  H01L29/7889

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.