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    Methods for migrating information stored in memory using an intermediate depth map
    33.
    发明授权
    Methods for migrating information stored in memory using an intermediate depth map 有权

    公开(公告)号：US10817412B2

    公开(公告)日：2020-10-27

    申请号：US16030600

    申请日：2018-07-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： David A. Roberts ,  J. Thomas Pawlowski ,  Robert Walker

    IPC: G06F12/02 ,  G06F13/16

    Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a memory configured to store information. Memory of the memory is configured with two or more information depth maps. The example apparatus further includes a memory translation unit (MTU) configured to support an intermediate depth map of the memory during the migration of the information stored at the memory from a first information depth map of the two or more information depth maps to a second information depth map of the two or more information depth by maintaining mapping tables. The MTU is further configured to provide a mapped address associated with a requested address of a memory access request to the memory based on the mapping tables.

    Memory device command receiving and decoding methods
    36.
    发明授权
    Memory device command receiving and decoding methods 有权

    公开(公告)号：US10127969B2

    公开(公告)日：2018-11-13

    申请号：US15456164

    申请日：2017-03-10

    Applicant: Micron Technology, Inc.

    Inventor： Scott Smith ,  Duc Ho ,  J. Thomas Pawlowski

    IPC: G11C11/4076 ,  G06F3/06 ,  G11C11/406 ,  G11C11/408

    Abstract: Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

    METHOD AND DEVICE TO REDUCE POWER CONSUMPTION MANAGMENT OF A PATTERN-RECOGNITION PROCESSOR
    40.
    发明申请
    METHOD AND DEVICE TO REDUCE POWER CONSUMPTION MANAGMENT OF A PATTERN-RECOGNITION PROCESSOR 审中-公开
    降低图形识别处理器功耗管理的方法和设备

    公开(公告)号：US20160320829A1

    公开(公告)日：2016-11-03

    申请号：US15206844

    申请日：2016-07-11

    Applicant: Micron Technology, Inc.

    Inventor： J. Thomas Pawlowski

    IPC: G06F1/32 ,  G06N5/04

    CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/3206 ,  G06F7/02 ,  G06F2207/025 ,  G06N5/047

    Abstract: A device includes a pattern-recognition processor. The pattern recognition processor includes blocks, such that each of the blocks include a plurality of feature cells configured to analyze at least a portion of data to be analyzed and to selectively provide a result of the analysis. The pattern recognition processor also includes block deactivation logic configured to dynamically power-down the block.

    Abstract translation: 一种设备包括模式识别处理器。 模式识别处理器包括块，使得每个块包括被配置成分析待分析的数据的至少一部分的多个特征单元并且选择性地提供分析的结果。 模式识别处理器还包括被配置为动态地关闭该块的块去激活逻辑。

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