公开(公告)号：US10896722B1

公开(公告)日：2021-01-19

申请号：US16684835

申请日：2019-11-15

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li ,  Charles L. Ingalls

IPC: G11C5/06 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/408

Abstract: Some embodiments include an integrated assembly having first memory cells in a first array and second memory cells in a second array. First and second digit lines extend along columns of the first and second arrays, respectively. The first digit lines are comparatively coupled with the second digit lines through sense-amplifier-circuitry. The sense-amplifier-circuitry is distributed amongst at least two patch locations. A first of the patch locations has a first portion of the sense-amplifier-circuitry and has a first local column-select-structure. A second of the patch locations has a second portion of the sense-amplifier-circuitry and has a second local column-select-structure. A column-select-bus extends from decoder-circuitry to the first and second local column-select-structures. The column-select-bus is selectively coupled to the first and second local column-select-structures through first and second switches, respectively.

公开(公告)号：US10770127B2

公开(公告)日：2020-09-08

申请号：US16268818

申请日：2019-02-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Shore ,  Jiyun Li

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/407

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for managing access counts of wordlines of a memory. Repeated access to an aggressor wordline may cause increased data degradation in nearby victim wordlines of the memory. The access count of a given wordline may be stored in counter memory cells positioned along that wordline. When the wordline is accessed, the counter memory cells may be read out to refresh circuit, which may determine the access count based on the values stored in the counter memory cells. If the access count is below a threshold, the access count may be incremented and written back to the counter memory cells. If the access count is above the threshold, the refresh circuit may signal that the accessed wordline is an aggressor, and may reset the value of the access count before writing it back to the counter memory cells.

公开(公告)号：US20200251158A1

公开(公告)日：2020-08-06

申请号：US16268818

申请日：2019-02-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Shore ,  Jiyun Li

IPC: G11C11/406 ,  G11C11/407 ,  G11C11/4076

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for managing access counts of wordlines of a memory. Repeated access to an aggressor wordline may cause increased data degradation in nearby victim wordlines of the memory. The access count of a given wordline may be stored in counter memory cells positioned along that wordline. When the wordline is accessed, the counter memory cells may be read out to refresh circuit, which may determine the access count based on the values stored in the counter memory cells. If the access count is below a threshold, the access count may be incremented and written back to the counter memory cells. If the access count is above the threshold, the refresh circuit may signal that the accessed wordline is an aggressor, and may reset the value of the access count before writing it back to the counter memory cells.

公开(公告)号：US12010831B2

公开(公告)日：2024-06-11

申请号：US17141426

申请日：2021-01-05

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Jiyun Li

IPC: G11C11/401 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  H10B12/00

CPC classification number: H10B12/50 ,  G11C11/401 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  H10B12/30

Abstract: Some embodiments include an integrated assembly having a memory array over a base. The memory array includes a three-dimensional arrangement of memory cells. Sense amplifiers are associated with the base and are directly under the memory array. Vertically-extending digit lines pass through the arrangement of the memory cells and are coupled with the sense amplifiers. Some embodiments include an integrated assembly having a memory bank containing 64 memory chunks arranged in a 16×4 configuration. Some embodiments include an integrated assembly having a memory bank which contains 512 megabytes divided amongst 64 memory chunks which each have 8 megabytes. The 64 memory chunks are arranged in a configuration having multiple rows which each contain a two or more of the memory chunks.

公开(公告)号：US20240013816A1

公开(公告)日：2024-01-11

申请号：US17811794

申请日：2022-07-11

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Jiyun Li

IPC: G11C7/08 ,  G11C7/12 ,  G11C7/10

CPC classification number: G11C7/08 ,  G11C7/12 ,  G11C7/1069

Abstract: Methods, systems, and devices for circuit for tracking access occurrences are described. For instance, a memory device may include a memory array with column lines extending in a first direction and row lines extending in a second direction. The memory device may include a set of sense amplifiers adjacent to the memory array in the first direction, where a first subset of the set of sense amplifiers is coupled with the first set of column lines and a second subset of the set of sense amplifiers is coupled with the second set of column lines. The memory device may include a circuit adjacent to the set of sense amplifiers along the second direction, where the circuit is configured to increment, based on the access operation for the row line, a value including the logic states read by the second subset of the set of sense amplifiers.

公开(公告)号：US11798610B2

公开(公告)日：2023-10-24

申请号：US17347957

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  Jiyun Li ,  Beau D. Barry ,  Matthew D. Jenkinson ,  Nathaniel J. Meier ,  Michael A. Shore ,  Adam J. Grenzebach ,  Dennis G. Montierth

IPC: G11C11/401 ,  G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40611 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/40618

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

公开(公告)号：US11581035B2

公开(公告)日：2023-02-14

申请号：US17184345

申请日：2021-02-24

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li ,  Toby D. Robbs

IPC: G11C7/10 ,  G11C11/4097 ,  G11C11/4096 ,  G11C11/408

Abstract: A memory device may include a memory array having a plurality of memory cells and a first column plane having multiple column select lines. The first column select lines of the first column plane may access a first set of the memory cells associated with the first column plane. Additionally, the memory device may include a second column plane having a multiple column select lines to access a second set of the memory cells associated with the second column plane. The memory device may also include a column select line shared between the first column plane and the second column plane. The column select line may access a third set of the memory cells associated with the first column plane and a fourth set of the memory cells associated with the second column plane.

公开(公告)号：US11550654B2

公开(公告)日：2023-01-10

申请号：US17100775

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Jiyun Li

IPC: G06F11/10 ,  G06K9/62 ,  G06F1/12 ,  G06F1/10

Abstract: Methods, apparatuses, and systems related to an apparatus are described. The apparatus may include (1) a fuse array configured to provide non-volatile storage of fuse data and (2) local latches configured to store the fuse data during runtime of the apparatus. The apparatus may further include an error processing circuit configured to determine error detection-correction data for the fuse data. The apparatus may subsequently broadcast data stored in the local latches to the error processing circuit to determine, using the error detection-correction data, whether the locally latched data has been corrupted. The error processing circuit may generate corrected data to replace the locally latched data based on determining corruption in the locally latched data.

公开(公告)号：US11347585B2

公开(公告)日：2022-05-31

申请号：US16926559

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li ,  Johnathan L. Gossi

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G11C29/10 ,  G06F11/30

Abstract: Methods, systems, and devices for a compression method for defect visibility in a memory device are described. A memory device may identify one or more errors associated with a set of memory cells of a memory array in the device based on a first set of data associated with the first set of memory cells. The memory device may generate an indication of a location of the one or more errors in the first set of memory cells and compress the first set of data to generate an error flag based on identifying the one or more errors. The memory device may output the error flag and the indication of the location based on generating the error flag and the indication.

公开(公告)号：US20210407583A1

公开(公告)日：2021-12-30

申请号：US17470883

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Jason M. Brown ,  Nathaniel J. Meier ,  Timothy B. Cowles ,  Jiyun Li

IPC: G11C11/406 ,  G11C11/408

Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/−1) at a faster rate than counts for more distant victim rows (e.g., +/−2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.