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公开(公告)号：US20230350574A1
公开(公告)日：2023-11-02
申请号：US17731100
申请日：2022-04-27
Applicant: Micron Technology, Inc.
Inventor： Bryan David Kerstetter , Donald M. Morgan , Alan J. Wilson , John David Porter , Jeffrey P. Wright
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F3/0676
Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.
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公开(公告)号：US20230178139A1
公开(公告)日：2023-06-08
申请号：US17922199
申请日：2020-05-29
Applicant: Micron Technology, Inc.
Inventor： Si Hong Kim , Ki-Jun Nam , Zhi Qi Huang , John David Porter
IPC: G11C11/4076
CPC classification number: G11C11/4076
Abstract: A system (100) for providing a timing signal with tunable temperature dependency in an electronic device may include a timing circuit (102) and an initial setting circuit (104). The timing circuit (102) may include a delay stage (106) and a gate stage (108). The delay stage (106) may be configured to receive an input signal and to produce a delayed signal by introducing a delay to the input signal. The gate stage (108) may be configured to receive the delayed signal and a threshold setting signal, to produce an output signal using the delayed signal and a logic threshold, and to set an initial value of the logic threshold according to the threshold setting signal. The initial setting circuit (104) may be configured to allow the threshold setting signal to be tuned for providing the time delay with a specified temperature dependency.
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公开(公告)号：US11658662B2
公开(公告)日：2023-05-23
申请号：US17078965
申请日：2020-10-23
Applicant: Micron Technology, inc.
Inventor： Hiroshi Akamatsu , Ki-Jun Nam , John David Porter
IPC: H03K19/00 , H03K19/096
CPC classification number: H03K19/0016 , H03K19/0963
Abstract: Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).
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公开(公告)号：US20210335396A1
公开(公告)日：2021-10-28
申请号：US16859417
申请日：2020-04-27
Applicant: Micron Technology, Inc.
Inventor： John David Porter , Suryanarayana B. Tatapudi
Abstract: Methods, systems, and devices are described for adjusting parameters of channel drivers based on temperature when a calibration component is unavailable. A memory device may determine whether a calibration component is available for use by the memory device. If not, the memory device may select an impedance setting for the driver that is based on an operating temperature of the memory device. A device or system may identify a temperature of a memory device, identify that a calibration component is unavailable to adjust a parameter of a driver of a data channel, select a value of the parameter based on the temperature and on identifying that the calibration component is unavailable, adjust the parameter of the driver of the data channel to the selected value, and transmit, by the driver operating using the selected value of the parameter, a signal over the channel.
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公开(公告)号：US10996694B2
公开(公告)日：2021-05-04
申请号：US16448162
申请日：2019-06-21
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Ki-Jun Nam , John David Porter
Abstract: A regulator includes an operational amplifier, a programmable offset voltage, and a circuit. The operational amplifier includes a non-inverting input, an inverting input, and an output. The programmable offset voltage is configured to cancel a built-in offset voltage of the regulator based on a code. The circuit is configured to set the code based on a sensed built-in offset voltage of the regulator in response to an offset cancellation calibration mode enable signal.
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Patent Agency Ranking
公开(公告)号：US20210044296A1
公开(公告)日：2021-02-11
申请号：US17078965
申请日：2020-10-23
Applicant: Micron Technology, Inc.
Inventor： Hiroshi Akamatsu , Ki-Jun Nam , John David Porter
IPC: H03K19/00 , H03K19/096
Abstract: Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).
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公开(公告)号：US09524759B2
公开(公告)日：2016-12-20
申请号：US14571735
申请日：2014-12-16
Applicant: Micron Technology, Inc.
Inventor： Ki-Jun Nam , John David Porter
IPC: G06F1/04 , G06F1/12 , G06F5/06 , G11C7/10 , H03K5/15 , G11C7/22 , H03K3/017 , G11C7/00 , G11C8/00 , H03L7/06 , G11C8/18
CPC classification number: G11C7/1012 , G11C7/00 , G11C7/10 , G11C7/106 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C8/00 , G11C8/18 , G11C2207/107 , H03K3/017 , H03K5/1502 , H03L7/06
Abstract: Apparatuses and methods for capturing data using a divided clock are described. An example apparatus includes a clock divider configured to receive a DQS signal, and to provide divided clock signals. A divided clock signal of the divided clock signals has a frequency that is less than a frequency of the DQS signal. The example apparatus further includes a command circuit configured to receive a command, and to assert one of a plurality of flag signals based on the divided clock signals and on a defined latency from a time of receipt of the command. The example apparatus further includes a data capture circuit configured serially receive data associated with the command and to provide deserialized data responsive to the divided clock signals. The data capture circuit is further configured to sort the deserialized data based on the asserted one of the plurality of flag signals to provide sorted data.
Abstract translation: 描述了使用分时钟捕获数据的装置和方法。 示例性装置包括被配置为接收DQS信号并且提供分频时钟信号的时钟分配器。 分频时钟信号的分频时钟信号的频率小于DQS信号的频率。 该示例设备还包括命令电路，其被配置为接收命令，并且基于所划分的时钟信号以及从接收到该命令的时间开始确定的延迟来断言多个标志信号之一。 该示例设备还包括数据捕获电路，其配置为串行地接收与该命令相关联的数据，并且响应于划分的时钟信号提供反序列化数据。 数据捕获电路还被配置为基于所述多个标志信号中的所述一个标记信号对反序列化数据进行排序以提供分类数据。
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公开(公告)号：US09490631B2
公开(公告)日：2016-11-08
申请号：US14275211
申请日：2014-05-12
Applicant: Micron Technology, Inc.
Inventor： Xiaofeng Fan , Michael Chaine , John David Porter
CPC classification number: H02H9/044 , H01L27/0248 , H01L27/0251 , H02H9/046 , H05K1/0259
Abstract: Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.
Abstract translation: 公开了用于保护电路免受过电压条件的设备和方法。 一个示例性设备包括耦合到要保护的电路的保护电路。 要保护的电路耦合到焊盘节点。 保护电路被配置为将电流从焊盘节点传导到参考电压节点，以保护电路免受超限电气状况的影响。 保护电路具有耦合到焊盘节点的触发电路，并被配置为响应于提供给具有超过触发电压的电压的焊盘节点的电压，触发分流电路以将电流从焊盘节点传导到参考电压节点。 在一些实施例中，触发电路与被保护的电路相匹配。
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公开(公告)号：US20250085867A1
公开(公告)日：2025-03-13
申请号：US18955719
申请日：2024-11-21
Applicant: Micron Technology, Inc.
Inventor： Bryan David Kerstetter , Donald M. Morgan , Alan J. Wilson , John David Porter , Jeffrey P. Wright
IPC: G06F3/06
Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.
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公开(公告)号：US12159039B2
公开(公告)日：2024-12-03
申请号：US17731100
申请日：2022-04-27
Applicant: Micron Technology, Inc.
Inventor： Bryan David Kerstetter , Donald M. Morgan , Alan J. Wilson , John David Porter , Jeffrey P. Wright
IPC: G06F3/06
Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.
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