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    Memory arrays and methods of forming memory arrays
    32.
    发明授权
    Memory arrays and methods of forming memory arrays 有权

    公开(公告)号：US09871078B2

    公开(公告)日：2018-01-16

    申请号：US15421855

    申请日：2017-02-01

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

    Abstract: Some embodiments include a memory array having a first memory cell adjacent to a second memory cell along a lateral direction. The second memory cell is vertically offset relative to the first memory cell. Some embodiments include a memory array having a series of data/sense lines extending along a first direction, a series of access lines extending along a second direction, and memory cells vertically between the access lines and data/sense lines. The memory cells are arranged in a grid having columns along the first direction and rows along the second direction. Memory cells in a common column and/or row as one another are arranged in two alternating sets, with a first set having memory cells at a first height and a second set having memory cells at a second height vertically offset relative to the first height. Some embodiments include methods of forming memory arrays.

    Memory Arrays and Methods of Forming Memory Arrays
    33.
    发明申请
    Memory Arrays and Methods of Forming Memory Arrays 有权
    内存数组和形成内存数组的方法

    公开(公告)号：US20170025477A1

    公开(公告)日：2017-01-26

    申请号：US14803303

    申请日：2015-07-20

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

    Abstract: Some embodiments include a memory array having a first memory cell adjacent to a second memory cell along a lateral direction. The second memory cell is vertically offset relative to the first memory cell. Some embodiments include a memory array having a series of data/sense lines extending along a first direction, a series of access lines extending along a second direction, and memory cells vertically between the access lines and data/sense lines. The memory cells are arranged in a grid having columns along the first direction and rows along the second direction. Memory cells in a common column and/or row as one another are arranged in two alternating sets, with a first set having memory cells at a first height and a second set having memory cells at a second height vertically offset relative to the first height. Some embodiments include methods of forming memory arrays.

    Abstract translation: 一些实施例包括具有沿着横向方向与第二存储器单元相邻的第一存储单元的存储器阵列。 第二存储单元相对于第一存储单元垂直偏移。 一些实施例包括具有沿着第一方向延伸的一系列数据/感测线的存储器阵列，沿第二方向延伸的一系列接入线以及在接入线和数据/感测线之间垂直的存储单元。 存储单元布置成具有沿着第一方向的列和沿着第二方向的列的网格。 公共列和/或行中的存储单元彼此排列成两个交替的组，其中第一组具有第一高度的存储单元，而第二组具有相对于第一高度垂直偏移的第二高度的存储单元。 一些实施例包括形成存储器阵列的方法。

    ANALOG STORAGE USING MEMORY DEVICE
    34.
    发明申请
    ANALOG STORAGE USING MEMORY DEVICE 有权

    公开(公告)号：US20240420786A1

    公开(公告)日：2024-12-19

    申请号：US18819191

    申请日：2024-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Innocenzo Tortorelli

    IPC: G11C27/00 ,  G06N3/065 ,  G06N3/08

    Abstract: Methods, systems, and devices for analog storing information are described herein. Such methods, systems and devices are suitable for synaptic weight storage in electronic neuro-biological mimicking architectures. A memory device may include a plurality of memory cells each respective memory cell in the plurality of memory cells with a respective programming sensitivity different from the respective programming sensitivity of other memory cells in the plurality. Memory cells may be provided on different decks of a multi-deck memory array. A storage element material of a respective memory cell may have a thickness and/or a composition different from another thickness or composition of a respective storage element material of another respective memory cell on a different deck in the multi-deck memory array. The memory device may further include reading circuitry configured to analogically read respective information programmed in the respective memory cells and to provide an output based on a combination of the respective information analogically read from the respective memory cells.

    Adaptive write operations for a memory device
    37.
    发明授权
    Adaptive write operations for a memory device 有权

    公开(公告)号：US11942183B2

    公开(公告)日：2024-03-26

    申请号：US17502481

    申请日：2021-10-15

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Richard K. Dodge ,  Innocenzo Tortorelli ,  Mattia Robustelli ,  Mario Allegra

    IPC: G11C7/00 ,  G11C7/10

    CPC classification number: G11C7/1096 ,  G11C7/1051

    Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).

    Memory cells for storing operational data
    38.
    发明授权
    Memory cells for storing operational data 有权

    公开(公告)号：US11783897B2

    公开(公告)日：2023-10-10

    申请号：US17875001

    申请日：2022-07-27

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Anna Maria Conti ,  Innocenzo Tortorelli

    IPC: G11C7/00 ,  G11C16/10 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26

    CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404

    Abstract: Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.

    MEMORY CELLS FOR STORING OPERATIONAL DATA
    40.
    发明申请
    MEMORY CELLS FOR STORING OPERATIONAL DATA 有权

    公开(公告)号：US20230019954A1

    公开(公告)日：2023-01-19

    申请号：US17875001

    申请日：2022-07-27

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Anna Maria Conti ,  Innocenzo Tortorelli

    IPC: G11C16/10 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26

    Abstract: Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.

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