公开(公告)号：US20210134364A1

公开(公告)日：2021-05-06

申请号：US17037495

申请日：2020-09-29

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Nathan Joseph Sirocka ,  Byung Sick Moon ,  Jeffrey Edward Koelling

IPC: G11C13/00

Abstract: A timing control circuit in an integrated circuit memory device. The circuit has an input line, a first output line and a second output line. The input line configured to receive a control signal for the timing control circuit to generate, a first selection input on the first output line and a second selection input on the second output line. In response to the control signal transitioning from a first state to a second state, the first selection input completes a first transition before the second selection input starts a second transition (e.g., for selection between 0V and −4.5V); and in response to the control signal transitioning from the second state to the first state, the second selection input completes a third transition before the first selection input starts fourth transition (e.g., for selection between 5V and 1.2V). The sequential transitions avoid simultaneous selection of 5V and −4.5V.

公开(公告)号：US20210118501A1

公开(公告)日：2021-04-22

申请号：US16660594

申请日：2019-10-22

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Nathan Joseph Sirocka ,  Hari Giduturi

IPC: G11C13/00

Abstract: An integrated circuit memory device having: a memory cell; and a voltage driver of depletion type connected to the memory cell. In a first polarity, the voltage driver is powered by a negative voltage relative to ground to drive a negative selection voltage or a first de-selection voltage; In a second polarity, the voltage driver is powered by a positive voltage relative to ground to drive a positive selection voltage or a second de-selection voltage. The voltage driver is configured to transition between the first polarity and the second polarity. During the transition, the voltage driver is configured to have a control voltage swing for outputting de-selection voltages smaller than a control voltage swing for output selection voltages.

公开(公告)号：US10410718B2

公开(公告)日：2019-09-10

申请号：US16190563

申请日：2018-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Hari Giduturi ,  Mingdong Cui

IPC: G11C11/00 ,  G11C13/00 ,  G11C29/50

Abstract: Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell.

公开(公告)号：US08963532B2

公开(公告)日：2015-02-24

申请号：US14222861

申请日：2014-03-24

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Xinwei Guo

IPC: G05F1/10 ,  G11C13/00 ,  G11C7/14

CPC classification number: G11C13/004 ,  G11C7/14

Abstract: Example reference current distribution circuitry described herein include current mirrors having resistive elements of varying sizes between gate nodes of sense amplifier transistors along a voltage distribution line. Examples of counter coupling capacitances which may be coupled to the gate nodes of sense amplifier transistors are also described.

Abstract translation: 本文描述的示例性参考电流分配电路包括电流镜，其具有沿着电压分配线的读出放大器晶体管的栅极节点之间具有不同大小的电阻元件。 还描述了可耦合到读出放大器晶体管的栅极节点的计数耦合电容的示例。

公开(公告)号：US20250006249A1

公开(公告)日：2025-01-02

申请号：US18765076

申请日：2024-07-05

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui

IPC: G11C11/408 ,  H10B80/00

Abstract: Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

公开(公告)号：US20240395339A1

公开(公告)日：2024-11-28

申请号：US18792404

申请日：2024-08-01

Applicant: Micron Technology, Inc.

Inventor： Kijun Nam ,  Mingdong Cui

IPC: G11C16/30 ,  G11C5/14 ,  G11C16/12 ,  G11C16/26 ,  G11C16/34

Abstract: In some aspects, the techniques described herein relate to a circuit including: a memory cell; a source follower, a source terminal of the source follower communicatively coupled to the memory cell; a voltage source; an operational amplifier, a non-inverting input of the operational amplifier communicatively coupled to the voltage source; and a replica source follower, a gate of the replica source follower communicatively coupled to an output of the operational amplifier and a source terminal of the replica source follower communicatively coupled to an inverting input of the operational amplifier via a feedback loop.

公开(公告)号：US11710528B2

公开(公告)日：2023-07-25

申请号：US17487792

申请日：2021-09-28

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Nevil N. Gajera ,  Hongmei Wang ,  Mingdong Cui

IPC: G11C7/00 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/3404 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: Methods, systems, and devices for data-based polarity write operations are described. A write command may cause a set of data to be written to a set of memory cells. To write the set of data, a write operation that applies voltages across the memory cells based on a logic state of data to be written to the memory cells may be used. During a first interval of the write operation, a voltage may be applied across a memory cell based on a logic state of a data bit to be written to the memory cell. During a second interval of the write operation, a voltage may be applied across the memory cell based on an amount of charge conducted by the memory cell during the first interval.

公开(公告)号：US20230115339A1

公开(公告)日：2023-04-13

申请号：US17496667

申请日：2021-10-07

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Hongmei Wang ,  Hari Giduturi

IPC: G11C13/00

Abstract: Systems, methods, and apparatus related to selecting memory cells in a memory array of a memory device. In one approach, bias circuitry generates a voltage on an access line used to select a memory cell for programming. During programming, a controller connects a boost capacitor to the access line by controlling a switch. Connecting the boost capacitor causes an increase in the rate of discharge of the access line (e.g., discharge of a word line to a negative voltage). After programming, the controller disconnects the boost capacitor from the access line, and the boost capacitor is pre-charged in preparation for a next programming operation (e.g., on the same or a different memory cell).

公开(公告)号：US11605425B2

公开(公告)日：2023-03-14

申请号：US17350422

申请日：2021-06-17

Applicant: Micron Technology, Inc.

Inventor： Nathan Joseph Sirocka ,  Mingdong Cui ,  Jeffrey Edward Koelling

IPC: G11C11/00 ,  G11C13/00

Abstract: A decoder in an integrated circuit memory device having: a positive section having a first input line; a negative section having a second input line; and an output line connected from both the positive section and the negative section to a voltage driver connected to a memory cell. The positive section and the negative section are controlled by a polarity control signal. When the polarity control signal indicates positive polarity, the positive section drives the output line according to signals received in the first input line; and when the polarity control signal indicates negative polarity, the negative section drives the output line according to signals received in the second input line.

公开(公告)号：US20220415395A1

公开(公告)日：2022-12-29

申请号：US17865248

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： Joemar Sinipete ,  John Christopher Sancon ,  Mingdong Cui

IPC: G11C13/00

Abstract: Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells may be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation may be performed. During a refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) may be applied to the one or more memory cells.