公开(公告)号：US20220230962A1

公开(公告)日：2022-07-21

申请号：US17666093

申请日：2022-02-07

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Christian George Emor ,  Travis Rampton ,  Everett Allen McTeer ,  Rita J. Klein

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/11582 ,  H01L23/532 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/528

Abstract: Described are methods for forming a tungsten conductive structure over a substrate, such as a semiconductor substrate. Described examples include forming a silicon-containing material, such as a doped silicon-containing material, over a supporting structure. The silicon-containing material is then subsequently converted to a tungsten seed material containing the dopant material. A tungsten fill material of lower resistance will then be formed over the tungsten seed material.

公开(公告)号：US20220059569A1

公开(公告)日：2022-02-24

申请号：US17517459

申请日：2021-11-02

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Daniel Billingsley ,  Indra V. Chary ,  Rita J. Klein

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/02 ,  H01L21/311 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Upper masses comprise first material laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks and second material laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory blocks longitudinally-between and under the upper masses. The second material is of different composition from that of the first material. The second material comprises insulative material. Other embodiments, including method, are disclosed.

公开(公告)号：US20210167020A1

公开(公告)日：2021-06-03

申请号：US16702222

申请日：2019-12-03

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Lifang Xu ,  Rita J. Klein ,  Xiao Li ,  Everett A. McTeer

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768

Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

公开(公告)号：US20200328284A1

公开(公告)日：2020-10-15

申请号：US16383862

申请日：2019-04-15

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Rita J. Klein ,  Everett A. McTeer ,  John Mark Meldrim

IPC: H01L29/49 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. The wordline levels include conductive regions which have a first metal-containing material and a second metal-containing material. The first metal-containing material at least partially surrounds the second metal-containing material. The first metal-containing material has a different crystallinity than the second metal-containing material. In some embodiments the first metal-containing material is substantially amorphous, and the second metal-containing material has a mean grain size within a range of from greater than or equal to about 5 nm to less than or equal to about 200 nm. Charge-storage regions are adjacent the wordline levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US10438968B2

公开(公告)日：2019-10-08

申请号：US15924143

申请日：2018-03-16

Applicant: Micron Technology, Inc.

Inventor： John M. Meldrin ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

IPC: H01L27/115 ,  H01L27/11582 ,  H01L29/49 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/28

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

公开(公告)号：US20190280007A1

公开(公告)日：2019-09-12

申请号：US16413498

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11524 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11556

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

公开(公告)号：US09935120B2

公开(公告)日：2018-04-03

申请号：US15049097

申请日：2016-02-21

Applicant: Micron Technology, Inc.

Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

IPC: H01L27/115 ,  H01L27/11582 ,  H01L29/49 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28097 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4975

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

公开(公告)号：US20160172373A1

公开(公告)日：2016-06-16

申请号：US15049097

申请日：2016-02-21

Applicant: Micron Technology, Inc.

Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/28097 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4975

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

Abstract translation: 一些实施例包括具有交替的第一和第二电平的堆叠的存储器阵列。 通道材料柱延伸通过堆叠，并且垂直堆叠的存储器单元串沿着通道材料柱。 一个共同的来源在堆叠下，并且电耦合到通道材料柱。 普通源在金属硅化物上方具有导电保护材料，并且直接抵抗金属硅化物，导电保护材料是金属硅化物以外的组合物。 一些实施例包括制造集成结构的方法。

公开(公告)号：US09287379B2

公开(公告)日：2016-03-15

申请号：US14281569

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

IPC: H01L27/115 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28097 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4975

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

Abstract translation: 一些实施例包括具有交替的第一和第二电平的堆叠的存储器阵列。 通道材料柱延伸通过堆叠，并且垂直堆叠的存储器单元串沿着通道材料柱。 一个共同的来源在堆叠下，并且电耦合到通道材料柱。 普通源在金属硅化物上方具有导电保护材料，并且直接抵抗金属硅化物，导电保护材料是金属硅化物以外的组合物。 一些实施例包括制造集成结构的方法。

公开(公告)号：US08962431B2

公开(公告)日：2015-02-24

申请号：US14157192

申请日：2014-01-16

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  John Mark Meldrim ,  Rita J. Klein

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/283

CPC classification number: H01L21/28097 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/32134 ,  H01L21/32139

Abstract: A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over silicon and a second stack having second metal over silicon. The first and second metals are of different compositions. The substrate is subjected to conditions which react the second metal with the silicon in the second stack to form metal silicide-comprising material from the second stack. The first metal between the second metal and the silicon in the first stack precludes formation of a silicide comprising the second metal and silicon from the first stack. After forming the metal silicide-comprising material, the first metal, the second metal and the metal silicide-comprising material are subjected to an etching chemistry that etches at least some remaining of the first and second metals from the substrate selectively relative to the metal silicide-comprising material.

Abstract translation: 一种形成含金属硅化物的材料的方法包括形成衬底，该衬底包括具有超过硅的第一金属上的第二金属的第一堆叠和在硅上的第二金属的第二叠层。 第一和第二种金属具有不同的组成。 基板经受使第二金属与第二堆叠中的硅反应以形成来自第二堆叠的含金属硅化物的材料的条件。 第一堆叠中的第二金属和硅之间的第一金属阻止从第一堆叠形成包括第二金属和硅的硅化物。 在形成含金属硅化物的材料之后，对第一金属，第二金属和含金属硅化物的材料进行蚀刻化学，从而选择性地相对于金属硅化物从衬底中蚀刻至少一些剩余的第一和第二金属 令人惊奇的材料。