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公开(公告)号：US20210111706A1
公开(公告)日：2021-04-15
申请号：US17086792
申请日：2020-11-02
Applicant: Micron Technology, Inc.
Inventor： Yasuo Satoh , Hiroki Takahashi , Shuichi Tsukada , Yuan He
Abstract: A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.
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公开(公告)号：US10886898B1
公开(公告)日：2021-01-05
申请号：US16598964
申请日：2019-10-10
Applicant: Micron Technology, Inc.
Inventor： Yasuo Satoh , Hiroki Takahashi , Shuichi Tsukada , Yuan He
Abstract: A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.
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公开(公告)号：US20200302977A1
公开(公告)日：2020-09-24
申请号：US16357085
申请日：2019-03-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shuichi Tsukada
Abstract: Disclosed herein is an apparatus that includes first and second signal lines; a first differential amplifier having an inverting input node receiving an input signal, a non-inverting input node receiving a reference potential, and an output node connected to the first signal line; a second differential amplifier having an inverting input node receiving the reference potential a non-inverting input node receiving the input signal, and an output node connected to the second signal line, a level shift circuit cross-coupled to the first and second signal lines; a first replica circuit connected to the first signal line; a second replica circuit connected to the second signal line; and a first switch circuit configured to activate one of the level shift circuit, the first replica circuit, and the second replica circuit.
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公开(公告)号：US20200052698A1
公开(公告)日：2020-02-13
申请号：US16656415
申请日：2019-10-17
Applicant: Micron Technology, Inc.
Inventor： Tetsuya Arai , Shuichi Tsukada , Junki Taniguchi
Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.
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Patent Agency Ranking
公开(公告)号：US10511306B2
公开(公告)日：2019-12-17
申请号：US15220310
申请日：2016-07-26
Applicant: Micron Technology, Inc.
Inventor： Tetsuya Arai , Shuichi Tsukada , Junki Taniguchi
Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.
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公开(公告)号：US10373655B2
公开(公告)日：2019-08-06
申请号：US15833643
申请日：2017-12-06
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kenji Asaki , Shuichi Tsukada , Sachiko Edo
Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. An example apparatus includes a power supply configured to provide a supply voltage and further includes a bias circuit coupled to the power supply to produce a bias current. The bias circuit is configured to decrease the bias current as the supply voltage increases from a first value to a second value. The bias circuit continues to decrease the bias current as the supply voltage further increases from the second value in a first operation mode. The bias circuit also prevents the bias current from decreasing against a further increase of the supply voltage from the second value in a second operation mode.
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37.发明申请公开(公告)号：US20190172505A1
公开(公告)日：2019-06-06
申请号：US15833643
申请日：2017-12-06
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kenji Asaki , Shuichi Tsukada , Sachiko Edo
CPC classification number: G11C5/147 , G05F3/24 , G11C7/1084 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C11/4074 , G11C11/4076 , G11C11/4093 , G11C29/46 , G11C29/50 , G11C2029/5004 , G11C2029/5006
Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. An example apparatus includes a power supply configured to provide a supply voltage and further includes a bias circuit coupled to the power supply to produce a bias current. The bias circuit is configured to decrease the bias current as the supply voltage increases from a first value to a second value. The bias circuit continues to decrease the bias current as the supply voltage further increases from the second value in a first operation mode. The bias circuit also prevents the bias current from decreasing against a further increase of the supply voltage from the second value in a second operation mode.
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公开(公告)号：US09911471B1
公开(公告)日：2018-03-06
申请号：US15432864
申请日：2017-02-14
Applicant: Micron Technology, Inc.
Inventor： Shuichi Tsukada
CPC classification number: G11C7/1084 , G11C5/14 , G11C7/02 , G11C7/065 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C11/4074 , G11C11/4093
Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.
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公开(公告)号：US20170353183A1
公开(公告)日：2017-12-07
申请号：US15220310
申请日：2016-07-26
Applicant: Micron Technology, Inc.
Inventor： Tetsuya Arai , Shuichi Tsukada , Junki Taniguchi
IPC: H03K19/00
Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.
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