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    TESTING FOR MEMORY DEVICES USING DEDICATED COMMAND AND ADDRESS CHANNELS
    31.
    发明公开
    TESTING FOR MEMORY DEVICES USING DEDICATED COMMAND AND ADDRESS CHANNELS 审中-公开

    公开(公告)号：US20240281350A1

    公开(公告)日：2024-08-22

    申请号：US18581189

    申请日：2024-02-19

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Hanna

    IPC: G06F11/263

    CPC classification number: G06F11/263

    Abstract: Methods, systems, and devices for improved testing for memory devices using dedicated command and address (CA) channels are described. A memory system associated with the memory devices may include a buffer configured to store a channel select indicator that indicates which CA channel to be utilized for various access commands associated with the memory devices. The memory system may utilize headers to facilitate the data transfers between the associated memory devices and testing system via the indicated CA channel using the buffer. The memory system may detect a select chip enable command on the CA channel and may subsequently store the channel select indicator in the buffer. The memory system may then detect data on the dedicated CA channel and subsequently read the stored channel select indicator from the buffer. The memory system may then erase the channel select indicator from the buffer, after receiving a select chip terminate command.

    HOST ASSISTED LINK START
    32.
    发明公开
    HOST ASSISTED LINK START 审中-公开

    公开(公告)号：US20240241793A1

    公开(公告)日：2024-07-18

    申请号：US18535553

    申请日：2023-12-11

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Hanna

    IPC: G06F11/14 ,  G06F1/28

    CPC classification number: G06F11/142 ,  G06F1/28

    Abstract: Methods, systems, and devices for host assisted link start are described. A memory device may receive, from a host device, a first request message for a recovery configuration associated with power recovery of a peripheral of the memory device. The memory device may transmit, to the host device based at least in part on the first request message, a first response message including the recovery configuration associated with the power recovery of the peripheral of the memory device. The recovery configuration may include parametric data associated with the peripheral of the memory device to store at the host device.

    LOW-POWER BOOT-UP FOR MEMORY SYSTEMS
    33.
    发明公开
    LOW-POWER BOOT-UP FOR MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20240045596A1

    公开(公告)日：2024-02-08

    申请号：US17881294

    申请日：2022-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Reshmi Basu ,  Jonathan S. Parry ,  David Aaron Palmer ,  Luca Porzio ,  Giuseppe Cariello ,  Stephen Hanna

    IPC: G06F3/06

    CPC classification number: G06F3/0617 ,  G06F3/0653 ,  G06F3/0679

    Abstract: Methods, systems, and devices for low-power boot-up for memory systems are described. A memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.

    INTEGRATED PIVOT TABLE IN A LOGICAL-TO-PHYSICAL MAPPING
    34.
    发明申请
    INTEGRATED PIVOT TABLE IN A LOGICAL-TO-PHYSICAL MAPPING 有权

    公开(公告)号：US20230111015A1

    公开(公告)日：2023-04-13

    申请号：US17971414

    申请日：2022-10-21

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe D'Eliseo ,  Luca Porzio ,  Stephen Hanna

    IPC: G06F3/06 ,  G06F12/10

    Abstract: Methods, systems, and devices for integrating a pivot table in a logical-to-physical mapping of a memory system are described. The memory system may receive a read command and read a first entry of a first subset of mapping and a second entry of a second subset of mapping. The second entry may include at least a portion of a pivot table associated with physical addresses of a non-volatile memory device. The memory system may retrieve data from a physical address identified in the pivot table, rather than access a different portion of the logical-to-physical mapping. The memory system may transmit, to a host system, the data retrieved from the physical address identified in the pivot table.

    SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES
    36.
    发明申请
    SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES 有权

    公开(公告)号：US20220214821A1

    公开(公告)日：2022-07-07

    申请号：US17702217

    申请日：2022-03-23

    Applicant: Micron Technology, Inc.

    Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Scott Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Chistian M. Gyllenskog ,  Kulachet Tanpairoj

    IPC: G06F3/06 ,  G06F12/02

    Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

    Facilitating sequential reads in memory sub-systems
    37.
    发明授权
    Facilitating sequential reads in memory sub-systems 有权

    公开(公告)号：US11200179B2

    公开(公告)日：2021-12-14

    申请号：US16801949

    申请日：2020-02-26

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Hanna ,  Nadav Grosz

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/14 ,  G06F1/24 ,  G06F21/79 ,  G06F12/06 ,  G06F12/02

    Abstract: An example memory subsystem includes a memory component and a processing device, operatively coupled to the memory component. The processing device is configured to receive a plurality of logical-to-physical (L2P) records, wherein an L2P record of the plurality of L2P records maps a logical block address to a physical address of a memory block on the memory component; determine a sequential assist value specifying a number of logical block addresses that are mapped to consecutive physical addresses sequentially following the physical address specified by the L2P record; generate a security token encoding the sequential assist value; and associate the security token with the L2P record.

    Creating high density logical to physical mapping
    40.
    发明授权
    Creating high density logical to physical mapping 有权

    公开(公告)号：US11940926B2

    公开(公告)日：2024-03-26

    申请号：US17663255

    申请日：2022-05-13

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Hanna

    IPC: G06F12/1009 ,  G06F12/02

    CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F2212/7201

    Abstract: Methods, systems, and devices for creating high density logical to physical mapping are described. A memory system may implement storage of mapping information to store the logical addresses and the corresponding physical addresses. A memory system may receive a command associated with data and a corresponding set of logical addresses, and in some cases the memory device may determine that the logical addresses are sequential. The memory device may generate and store a set of compressed entries in a macro level of the mapping information. When the memory system receives a command associated with an exception to the sequential logical addresses, the memory system may update an entry of the macro level to include a pointer to a set of entries in another level of the mapping information.

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