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    Device reset alert mechanism
    1.
    发明授权
    Device reset alert mechanism 有权

    公开(公告)号：US11994951B2

    公开(公告)日：2024-05-28

    申请号：US17738645

    申请日：2022-05-06

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Hanna

    IPC: G06F11/14 ,  G06F11/07 ,  G06F11/30

    CPC classification number: G06F11/1441 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/3037 ,  G06F11/3055 ,  G06F11/3058 ,  G06F2201/805

    Abstract: Methods, systems, and devices for device reset alert mechanism are described. The memory system may identify a fault condition associated with resetting the memory system and set, in a register associated with event alerts of the memory system, a first indication for a reset of the memory system. In some cases, the memory system may transmit a message that includes a second indication that the register associated with event alerts of the memory system has been changed based on setting the register. The memory system may reset one or more components of the memory system based on the first indication and the second indication.

    COMPRESSION AND DECOMPRESSION OF TRIM DATA
    2.
    发明公开
    COMPRESSION AND DECOMPRESSION OF TRIM DATA 审中-公开

    公开(公告)号：US20240053905A1

    公开(公告)日：2024-02-15

    申请号：US17888309

    申请日：2022-08-15

    Applicant: Micron Technology, Inc.

    Inventor： Reshmi Basu ,  Jonathan S. Parry ,  Giuseppe Cariello ,  Stephen Hanna

    IPC: G06F3/06

    CPC classification number: G06F3/0631 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0604

    Abstract: Methods, systems, and devices for compression and decompression of trim data are described. A memory system may store one or more trim settings to a volatile memory in a compressed manner, and may expand (e.g., decompress) the data as part of a write operation to a non-volatile memory (e.g., during a start-up procedure). For example, compressed (e.g., non-expanded) data including trim settings may be stored to a volatile memory, and a portion of the array of volatile memory cells may be temporarily allocated to expand the data (e.g., copy the data, invert the data, copy the inverted data). Once the data is expanded, it may be stored in the non-volatile memory, and the temporarily allocated portion of the array of volatile memory cells may be reallocated (e.g., allocated for another purpose). The expanded data may include multiple copies and inverted copies of the trim settings.

    TECHNIQUES TO PERFORM A WRITE OPERATION
    3.
    发明公开
    TECHNIQUES TO PERFORM A WRITE OPERATION 审中-公开

    公开(公告)号：US20230259304A1

    公开(公告)日：2023-08-17

    申请号：US17651214

    申请日：2022-02-15

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Hanna

    IPC: G06F3/06

    CPC classification number: G06F3/0656 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0688

    Abstract: Methods, systems, and devices for techniques to perform a write operation are described. In response to receiving a sequential write command from a host system, the memory system may determine non-linear offsets for a set of requests for portions of the data. The memory system may determine a first subset of the data that includes data segments having logical addresses with gaps corresponding to the offset between the data segments to store in a first memory device. The memory system may store the first subset in a buffer and program the first subset to the first memory device. Additionally, the memory system may determine a second subset of data that using the offset and may transmit a second set of requests for the second subset of data, which may be stored in the buffer and programmed to a second memory device.

    Low cost and low latency logical unit erase
    6.
    发明授权
    Low cost and low latency logical unit erase 有权

    公开(公告)号：US11347659B2

    公开(公告)日：2022-05-31

    申请号：US16227072

    申请日：2018-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Hanna

    IPC: G06F12/14 ,  G06F11/10 ,  G06F21/79 ,  H04L9/08 ,  G06F12/02 ,  G11C16/14 ,  G06F21/60 ,  H03M13/11

    Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to generate a scrambler seed and a logical block address (LBA) for a block of write data received via the communication interface, scramble the block of data using the scrambler seed, encrypt the scrambler seed and the LBA using an encryption key, initiate writing a scrambled block of data and encrypted LBA and scrambler seed to the memory array, and change the encryption key in response to an erase command received via the communication interface.

    FACILITATING SEQUENTIAL READS IN MEMORY SUB-SYSTEMS
    7.
    发明申请
    FACILITATING SEQUENTIAL READS IN MEMORY SUB-SYSTEMS 有权

    公开(公告)号：US20220058138A1

    公开(公告)日：2022-02-24

    申请号：US17521360

    申请日：2021-11-08

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Hanna ,  Nadav Grosz

    IPC: G06F12/14 ,  G06F1/24 ,  G06F12/02 ,  G06F12/06 ,  G06F21/79

    Abstract: An example memory subsystem includes a memory component and a processing device, operatively coupled to the memory component. The processing device is configured to receive a plurality of logical-to-physical (L2P) records, wherein an L2P record of the plurality of L2P records maps a logical block address to a physical address of a memory block on the memory component; determine a sequential assist value specifying a number of logical block addresses that are mapped to consecutive physical addresses sequentially following the physical address specified by the L2P record; generate a security token encoding the sequential assist value; and associate the security token with the L2P record.

    Storage device with test interface
    9.
    发明授权
    Storage device with test interface 有权

    公开(公告)号：US10930366B2

    公开(公告)日：2021-02-23

    申请号：US16514685

    申请日：2019-07-17

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Hanna

    IPC: G11C29/48 ,  G06F13/16

    Abstract: An example system comprises: a master bus electrically coupled to a master multiplexer controlled by a test mode signal selecting between a master physical interface (PHY) and a slave bus of a plurality of slave buses, wherein each slave bus is electrically coupled to a respective slave multiplexer controlled by the test mode signal selecting between a respective slave PHY and the master bus; a plurality of memory components, wherein each memory component of the plurality of memory components is electrically coupled to one of: the master bus or a slave bus of the plurality of slave buses; and a memory test interface electrically coupled to the master bus.

    SERIAL PASS-THROUGH TECHNIQUES FOR MEMORY DEVICE INTERFACES
    10.
    发明申请
    SERIAL PASS-THROUGH TECHNIQUES FOR MEMORY DEVICE INTERFACES 有权

    公开(公告)号：US20250118344A1

    公开(公告)日：2025-04-10

    申请号：US18774431

    申请日：2024-07-16

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Hanna ,  Jonathan S. Parry

    IPC: G11C7/10 ,  G11C29/52

    Abstract: Methods, systems, and devices for serial pass-through techniques for memory device interfaces are described. Memory interface circuitry may be configured to receive a command via a first interface having a first set of terminals to configure the memory interface circuitry for a pass-through mode. As part of the pass-through mode, the memory interface circuitry may receive data from an external device via the first interface and output the data to one or more memory devices via a second interface having a second set of terminals. In some examples, the received data may be associated with a write burst, in which the memory interface circuitry may serially receive multiple portions of the data to write to a buffer of the memory interface circuitry. After reaching a threshold quantity of data, the buffer may output the portions of the data to the one or more memory devices via the second interface.

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