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    FERROELECTRIC MEMORY CELL ACCESS
    33.
    发明申请
    FERROELECTRIC MEMORY CELL ACCESS 有权

    公开(公告)号：US20250014623A1

    公开(公告)日：2025-01-09

    申请号：US18777046

    申请日：2024-07-18

    Applicant: Micron Technology, Inc.

    Inventor： Umberto Di Vincenzo

    IPC: G11C11/22

    Abstract: Methods, systems, and devices for accessing a ferroelectric memory cell are described. In some examples, during a first portion of an access procedure, the voltages of a digit line and word line coupled with the memory cell may be increased while the voltage of a plate coupled with the memory cell is held constant, which may support sensing a logic state stored by the memory cell prior the access procedure, and which may result in a first logic state being written to the memory cell. A voltage of the plate may then be increased, and the digit line may then be coupled with the plate. Because the first logic state was previously written to the memory cell, a target logic state may not need to be subsequently written to the memory cell unless different than the first logic state.

    CURRENT REFERENCES FOR MEMORY CELLS
    34.
    发明公开
    CURRENT REFERENCES FOR MEMORY CELLS 审中-公开

    公开(公告)号：US20240203490A1

    公开(公告)日：2024-06-20

    申请号：US18590692

    申请日：2024-02-28

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Pierguido Garofalo ,  Umberto Di Vincenzo ,  Claudia Palattella

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C2013/0054

    Abstract: A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.

    CURRENT REFERENCES FOR MEMORY CELLS
    36.
    发明公开
    CURRENT REFERENCES FOR MEMORY CELLS 审中-公开

    公开(公告)号：US20230335191A1

    公开(公告)日：2023-10-19

    申请号：US17720957

    申请日：2022-04-14

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Pierguido Garofalo ,  Umberto Di Vincenzo ,  Claudia Palattella

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C2013/0054

    Abstract: A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.

    Methods and systems for improving access to memory cells
    38.
    发明授权
    Methods and systems for improving access to memory cells 有权

    公开(公告)号：US11705211B2

    公开(公告)日：2023-07-18

    申请号：US17415646

    申请日：2020-07-14

    Applicant: Micron Technology, Inc.

    Inventor： Riccardo Muzzetto ,  Umberto Di Vincenzo ,  Ferdinando Bedeschi

    IPC: G11C7/00 ,  G11C16/34 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26 ,  G11C29/52

    CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/22 ,  G11C16/26 ,  G11C16/3404 ,  G11C29/52

    Abstract: The present disclosure relates to a method for accessing an array of memory cells, including storing a set of user data in a plurality of memory cells, storing, in a portion of the array, additional information representative of a voltage difference between a first threshold voltage and a second threshold voltage of the memory cells programmed to a first logic state, applying to the array a read voltage to activate a first group of memory cells corresponding to a preset number of memory cells, determining that the first group of memory cells has been activated based on applying the read voltage, wherein the read voltage is equal to the first threshold voltage when the first group of memory cells has been activated, and based on the additional data information, applying the voltage difference to the array to activate a second group of memory cells programmed to the first logic state.

    System and method for reading memory cells
    39.
    发明授权
    System and method for reading memory cells 有权

    公开(公告)号：US11694748B2

    公开(公告)日：2023-07-04

    申请号：US17716716

    申请日：2022-04-08

    Applicant: Micron Technology, Inc.

    Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/003 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0045

    Abstract: A method, a circuit, and a system for reading memory cells. The method may include: applying a first voltage with a first polarity to a plurality of the memory cells; applying a second voltage with a second polarity to one or more of said plurality of the memory cells; applying at least a third voltage with the first polarity to one or more of said plurality of the memory cells; detecting electrical responses of memory cells to the first voltage, the second voltage, and the third voltage; and determining a logic state of respective memory cells based on the electrical responses of the memory cells to the first voltage, the second voltage, and the third voltage.

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