公开(公告)号：US20240063156A1

公开(公告)日：2024-02-22

申请号：US18380118

申请日：2023-10-13

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Thiagarajan Raman

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/433 ,  H01L21/56

CPC classification number: H01L24/06 ,  H01L23/296 ,  H01L24/05 ,  H01L23/4334 ,  H01L21/56 ,  H01L24/03 ,  H01L2924/35121 ,  H01L2224/06519 ,  H01L2224/05091

Abstract: Semiconductor devices including electrically-isolated extensions and associated systems and methods are disclosed herein. An electrically-isolated extension may be coupled to a corresponding connection pad that is attached to a surface of a device. The electrically-isolated extensions may extend at least partially through one or more layers at or near the surface and toward a substrate or an inner portion thereof.

公开(公告)号：US20240047260A1

公开(公告)日：2024-02-08

申请号：US17882399

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou

IPC: H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L21/6835 ,  H01L23/3171 ,  H01L24/05 ,  H01L24/06 ,  H01L24/80 ,  H01L24/08 ,  H01L25/0657 ,  H01L21/568 ,  H01L24/11 ,  H01L23/291

Abstract: Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a region of hydrophobic material electrically isolated from any circuitry of the first semiconductor device and configured to have a reduced bonding strength to a facing region relative to the dielectric-dielectric bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.

公开(公告)号：US20230260964A1

公开(公告)日：2023-08-17

申请号：US17711583

申请日：2022-04-01

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K. Street ,  Kunal R. Parekh

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor device having monolithic conductive cylinders, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, and a top dielectric layer. The conductive pad may be at a first surface of the semiconductor substrate. The opening may be ring-shaped and extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the top dielectric layer may cover the second surface and may fill the opening. A second ring-shaped opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

公开(公告)号：US20230260875A1

公开(公告)日：2023-08-17

申请号：US17670378

申请日：2022-02-11

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K. Street ,  Kunal R. Parekh

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L21/76877 ,  H01L25/0657 ,  H01L24/08 ,  H01L24/32 ,  H01L24/83 ,  H01L2225/06541 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2224/8319

Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

公开(公告)号：US20220406765A9

公开(公告)日：2022-12-22

申请号：US17133269

申请日：2020-12-23

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou

IPC: H01L25/18 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00

Abstract: Semiconductor device packages may include a bottom-most semiconductor die, at least one intermediate semiconductor die stacked over the bottom-most semiconductor die, and a top-most semiconductor die located on a side of a farthest intermediate semiconductor die from the bottom-most semiconductor die opposite the bottom-most semiconductor die. The bottom-most semiconductor die and each intermediate semiconductor die may include vias extending therethrough. The bottom-most semiconductor die may have a larger foot print than each intermediate semiconductor die and the top-most semiconductor die. A dielectric material may be located between each of the semiconductor dice, at least sections of the dielectric material extending contiguously from between adjacent semiconductor dice, over sidewalls thereof, and laterally beyond the lateral peripheries all but the bottom-most semiconductor die

公开(公告)号：US11302653B2

公开(公告)日：2022-04-12

申请号：US16993860

申请日：2020-08-14

Applicant: Micron Technology, Inc.

Inventor： Bret K. Street ,  Wei Zhou ,  Christopher J. Gambee ,  Jonathan S. Hacker ,  Shijian Luo

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

公开(公告)号：US11289360B2

公开(公告)日：2022-03-29

申请号：US16715540

申请日：2019-12-16

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz ,  Wei Zhou

IPC: H01L21/683 ,  H01L21/78 ,  H01L21/67

Abstract: Disclosed are methods and apparatus for protecting dielectric films on microelectronic components from contamination associated with singulation, picking and handling of singulated microelectronic components from a wafer for assembly with other components.

公开(公告)号：US11114415B2

公开(公告)日：2021-09-07

申请号：US16823028

申请日：2020-03-18

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/495 ,  H01L25/00 ,  H01L23/64 ,  H01L21/56 ,  H01L23/36

Abstract: A semiconductor device includes a first die; a second die attached over the first die; a metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level; wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.

公开(公告)号：US20210183682A1

公开(公告)日：2021-06-17

申请号：US16715540

申请日：2019-12-16

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz ,  Wei Zhou

IPC: H01L21/683 ,  H01L21/78 ,  H01L21/67

Abstract: Disclosed are methods and apparatus for protecting dielectric films on microelectronic components from contamination associated with singulation, picking and handling of singulated microelectronic components from a wafer for assembly with other components.

公开(公告)号：US10923448B2

公开(公告)日：2021-02-16

申请号：US15627314

申请日：2017-06-19

Applicant: Micron Technology, Inc.

Inventor： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768

Abstract: A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.