公开(公告)号：US20190221534A1

公开(公告)日：2019-07-18

申请号：US16360317

申请日：2019-03-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Chan Chen ,  Yueh-Chuan Lee

IPC分类号： H01L23/00 ,  H01L27/146

CPC分类号： H01L24/08 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L2224/02331 ,  H01L2224/02381 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/0508 ,  H01L2224/05083 ,  H01L2224/05088 ,  H01L2224/05089 ,  H01L2224/05091 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05554 ,  H01L2224/05562 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/013 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/00012

摘要： Some embodiments relate to a bond pad structure of an integrated circuit (IC). The bond structure includes a bond pad and an intervening metal layer positioned below the bond pad. The intervening metal layer has a first face and a second face. A first via layer is in contact with the first face of intervening metal layer. The first via layer has a first via pattern. The bond structure also includes a second via layer in contact with the second face of the intervening metal layer. The second via layer has a second via pattern that is different than first via pattern. The second via pattern includes a first group of elongated vias extending in parallel with one another in a first direction and a second group of vias in between the first group of elongated vias. The second group of vias extend in a second direction orthogonal to the first direction.

公开(公告)号：US20170330848A1

公开(公告)日：2017-11-16

申请号：US15154289

申请日：2016-05-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Chan Chen ,  Yueh-Chuan Lee

IPC分类号： H01L23/00 ,  H01L27/146

CPC分类号： H01L24/08 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L2224/02331 ,  H01L2224/02381 ,  H01L2224/03616 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05091 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/05573 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2224/45099

摘要： Some embodiments relate to a bond pad structure of an integrated circuit (IC). In one embodiment the bond structure includes a bond pad and an intervening metal layer positioned below the bond pad. The intervening metal layer has a first face and a second face. A first via layer is in contact with the first face of intervening metal layer. The first via layer has a first via pattern. The bond structure also includes a second via layer in contact with the second face of the intervening metal layer. The second via layer has a second via pattern that is different than first via pattern.

公开(公告)号：US09812416B2

公开(公告)日：2017-11-07

申请号：US15589027

申请日：2017-05-08

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jiun Yi Wu ,  Hsueh-Lung Cheng ,  Shou-Yi Wang

IPC分类号： H01L21/4763 ,  H01L23/00 ,  H01L23/522 ,  H01L21/66 ,  H01L21/768

CPC分类号： H01L24/03 ,  H01L21/76804 ,  H01L21/7685 ,  H01L21/76879 ,  H01L22/32 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/562 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/03416 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/0392 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05091 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2924/01029 ,  H01L2924/20643 ,  H01L2924/3512 ,  H01L2924/00014

摘要： A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer and a second dielectric layer. The metal trace is connected to a ball connection by a first via in the first dielectric layer and second via in the second dielectric layer. The metal trace is connected to a test pad at a connection point, where the connection point is under the first dielectric layer. The metal trace under at least the first dielectric layer and the second dielectric layer has increased stability and decreased susceptibility to cracking in least one of the ball connection, the connection point, the first via or the second via as compared to a metal trace that is not under at least a first dielectric layer and a second dielectric layer.

公开(公告)号：US20170133335A1

公开(公告)日：2017-05-11

申请号：US15336774

申请日：2016-10-27

申请人： NXP B.V.

发明人： Chi Ho Leung ,  Pompeo V. Umali ,  Shun Tik Yeung ,  Wai (Kan Wae) Lam

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48

CPC分类号： H01L24/05 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/562 ,  H01L24/03 ,  H01L25/0657 ,  H01L2224/03011 ,  H01L2224/03013 ,  H01L2224/03424 ,  H01L2224/03464 ,  H01L2224/036 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05091 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2924/013

摘要： A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, one or more contacts located on the major surface and an encapsulant covering at least the major surface. A peripheral edge of each contact defines a contact area on the major surface. The device also includes one or more bond pads located outside the encapsulant. Each bond pad is electrically connected to a respective contact located on the major surface of the substrate by a respective metal filled via that passes through the encapsulant. A sidewall of each respective metal filled via, at the point at which it meets the respective contact, falls inside the contact area defined by the respective contact when viewed from above the major surface of the substrate, whereby none of the metal filling each respective via extends outside the contact area of each respective contact.

公开(公告)号：US11824025B2

公开(公告)日：2023-11-21

申请号：US17408343

申请日：2021-08-20

申请人： Micron Technology, Inc.

发明人： Wei Zhou ,  Thiagarajan Raman

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/433

CPC分类号： H01L24/06 ,  H01L21/56 ,  H01L23/296 ,  H01L23/4334 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05091 ,  H01L2224/06519 ,  H01L2924/35121

摘要： Semiconductor devices including electrically-isolated extensions and associated systems and methods are disclosed herein. An electrically-isolated extension may be coupled to a corresponding connection pad that is attached to a surface of a device. The electrically-isolated extensions may extend at least partially through one or more layers at or near the surface and toward a substrate or an inner portion thereof.

公开(公告)号：US20180286836A1

公开(公告)日：2018-10-04

申请号：US15921563

申请日：2018-03-14

申请人： Silicon Storage Technology, Inc.

发明人： Justin Hiroki Sato ,  Bomy Chen ,  Walter Lundy

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0217 ,  H01L2224/0219 ,  H01L2224/04042 ,  H01L2224/05091 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/16502 ,  H01L2224/48091 ,  H01L2224/81143 ,  H01L2224/81805 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/07025 ,  H01L2224/45099

摘要： A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.

公开(公告)号：US20170243842A1

公开(公告)日：2017-08-24

申请号：US15589027

申请日：2017-05-08

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jiun Yi WU ,  Hsueh-Lung CHENG ,  Shou-Yi WANG

IPC分类号： H01L23/00 ,  H01L21/66 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L24/03 ,  H01L21/76804 ,  H01L21/7685 ,  H01L21/76879 ,  H01L22/32 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/562 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/03416 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/0392 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05091 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2924/01029 ,  H01L2924/20643 ,  H01L2924/3512 ,  H01L2924/00014

摘要： A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer and a second dielectric layer. The metal trace is connected to a ball connection by a first via in the first dielectric layer and second via in the second dielectric layer. The metal trace is connected to a test pad at a connection point, where the connection point is under the first dielectric layer. The metal trace under at least the first dielectric layer and the second dielectric layer has increased stability and decreased susceptibility to cracking in least one of the ball connection, the connection point, the first via or the second via as compared to a metal trace that is not under at least a first dielectric layer and a second dielectric layer.

公开(公告)号：US20170194273A1

公开(公告)日：2017-07-06

申请号：US15156764

申请日：2016-05-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： SHENG-CHAU CHEN ,  SHIH-PEI CHOU ,  MING-JHE LEE ,  KUO-MING WU ,  CHENG-HSIEN CHOU ,  CHENG-YUAN TSAI ,  YEUR-LUEN TU

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/05 ,  H01L23/481 ,  H01L24/02 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05019 ,  H01L2224/05082 ,  H01L2224/05088 ,  H01L2224/05091 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/80 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L21/304 ,  H01L21/76898 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/00012

摘要： The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.

公开(公告)号：US20130134563A1

公开(公告)日：2013-05-30

申请号：US13308249

申请日：2011-11-30

申请人： Yao-Chun Chuang ,  Chang-Chia Huang ,  Tsung-Shu Lin ,  Chen-Cheng Kuo ,  Chen-Shien Chen

发明人： Yao-Chun Chuang ,  Chang-Chia Huang ,  Tsung-Shu Lin ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC分类号： H01L23/58 ,  H01L21/28 ,  H01L23/48

CPC分类号： H01L24/11 ,  H01L23/293 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05022 ,  H01L2224/05086 ,  H01L2224/05091 ,  H01L2224/05124 ,  H01L2224/05541 ,  H01L2224/05572 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer.

摘要翻译： 结构包括形成在接合焊盘下方的顶部金属连接器。 接合焊盘由第一钝化层和第二钝化层包围。 聚合物层进一步形成在第二钝化层上。 第一钝化层中的开口的尺寸小于顶部金属连接器的尺寸。 顶部金属连接器的尺寸小于第二钝化层中的开口的尺寸和聚合物层中的开口的尺寸。

公开(公告)号：US20240063156A1

公开(公告)日：2024-02-22

申请号：US18380118

申请日：2023-10-13

申请人： Micron Technology, Inc.

发明人： Wei Zhou ,  Thiagarajan Raman

IPC分类号： H01L23/00 ,  H01L23/29 ,  H01L23/433 ,  H01L21/56

CPC分类号： H01L24/06 ,  H01L23/296 ,  H01L24/05 ,  H01L23/4334 ,  H01L21/56 ,  H01L24/03 ,  H01L2924/35121 ,  H01L2224/06519 ,  H01L2224/05091

摘要： Semiconductor devices including electrically-isolated extensions and associated systems and methods are disclosed herein. An electrically-isolated extension may be coupled to a corresponding connection pad that is attached to a surface of a device. The electrically-isolated extensions may extend at least partially through one or more layers at or near the surface and toward a substrate or an inner portion thereof.