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    Performing select gate integrity checks to identify and invalidate defective blocks
    32.
    发明授权
    Performing select gate integrity checks to identify and invalidate defective blocks 有权

    公开(公告)号：US11854644B2

    公开(公告)日：2023-12-26

    申请号：US17550462

    申请日：2021-12-14

    Applicant: Micron Technology, Inc.

    Inventor： Zhongguang Xu ,  Zhenlei Shen ,  Murong Lang

    IPC: G11C16/34 ,  G11C29/50 ,  G06F3/06

    CPC classification number: G11C29/50004 ,  G06F3/0679

    Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a parameter value of a select gate associated with a first set of memory cells; responsive to determining that the parameter value satisfies a threshold criterion, marking the first block in a grown bad block (GBB) data structure; performing one or more pulse operations on the first block to invalidate data stored on the block; receiving, from a host system, an enhanced erase command referencing a second block; and responsive to determining that the second block is marked in the GBB data structure, discarding the enhanced erase command.

    Adjusting read-level thresholds based on write-to-write delay
    36.
    发明授权
    Adjusting read-level thresholds based on write-to-write delay 有权

    公开(公告)号：US11742029B2

    公开(公告)日：2023-08-29

    申请号：US17402279

    申请日：2021-08-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhongguang Xu ,  Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

    IPC: G11C16/30 ,  G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G11C16/32

    CPC classification number: G11C16/26 ,  G11C16/102 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3404

    Abstract: A method includes performing a first write operation that writes data to a first memory unit of a group of memory units in a memory device, determining a write-to-write (W2W) delay based on a time difference between the first write operation and a second write operation on a memory unit in the group of memory units, wherein the second write operation occurred prior to the first write operation, identifying a threshold time criterion that is satisfied by the W2W delay, identifying a first read voltage level associated with the threshold time criterion, and associating the first read voltage level with a second memory unit of the group of memory units. The second memory unit can be associated with a second read voltage level that satisfies a selection criterion based on a comparison of the second read voltage level to the first read voltage level.

    MANAGING A HYBRID ERROR RECOVERY PROCESS IN A MEMORY SUB-SYSTEM
    38.
    发明申请
    MANAGING A HYBRID ERROR RECOVERY PROCESS IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20230069559A1

    公开(公告)日：2023-03-02

    申请号：US17462605

    申请日：2021-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Zhongguang Xu ,  Jian Huang ,  Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

    IPC: G06F3/06

    Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is receive. A request type associated with the memory access operation is determined. In response to determining that the request type associated with the request type associated with the memory access operation is a first request type, an error recovery operation associated with the first request type is performed. In response to determining that the request type associated with the memory access operation is a second request type, an error recovery operation associated with the second request type is performed.

    RATING MEMORY DEVICES BASED ON PERFORMANCE METRICS FOR VARIOUS TIMING MARGIN PARAMETER SETTINGS
    40.
    发明申请
    RATING MEMORY DEVICES BASED ON PERFORMANCE METRICS FOR VARIOUS TIMING MARGIN PARAMETER SETTINGS 有权

    公开(公告)号：US20220137854A1

    公开(公告)日：2022-05-05

    申请号：US17088280

    申请日：2020-11-03

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Murong Lang ,  Jian Huang ,  Zhongguang Xu ,  Zhenming Zhou

    IPC: G06F3/06

    Abstract: An operation timing condition associated with a memory device to be installed at a memory sub-system is determined. The memory device can include a cross-point array of non-volatile memory cells. The operation timing condition corresponds to a first operation delay timing margin setting for the cross-point array of non-volatile memory cells. A first set of memory access operations is performed at the cross-point array of non-volatile memory cells according to a second operation delay timing margin setting that is lower than the first operation delay timing margin setting. A first number of errors that occurred during performance of the first set of memory access operations is determined. In response to a determination that the first number of errors satisfies an error condition, a first quality rating is assigned for the memory device. In response to a determination that the first number of errors does not satisfy the error criterion, further testing is performed for the cross-point array of non-volatile memory cells based on one or more power level settings.

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