公开(公告)号：US10937832B2

公开(公告)日：2021-03-02

申请号：US16014346

申请日：2018-06-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Hsiang-Lan Lung

IPC: H01L27/105 ,  H01L27/24 ,  G11C13/00 ,  H01L45/00

Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a confined cell structure in series, and having sides aligned within the cross-point area of the corresponding cross-point, the confined cell structure including surfactant spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the surfactant spacers. The memory cells can be operated as multi-level cells in a 3D array.

公开(公告)号：US10283519B2

公开(公告)日：2019-05-07

申请号：US14665103

申请日：2015-03-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai

IPC: H01L29/66 ,  H01L29/04 ,  H01L29/16 ,  H01L29/24 ,  H01L29/423 ,  H01L29/792 ,  H01L27/115 ,  H01L21/31 ,  H01L21/311 ,  H01L21/306 ,  H01L21/465 ,  H01L21/469 ,  H01L27/11582 ,  H01L21/4757 ,  H01L27/11565 ,  H01L21/441 ,  H01L21/28 ,  H01L21/768

Abstract: A memory device including a substrate, at least one first stacked structure and at least one second stacked structure disposed on the substrate is provided. The first stacked structure includes a plurality of alternately stacked metal layers and oxide layers. The second stacked structure is disposed adjacent to the first stacked structure and includes a plurality of alternately stacked semiconductor layers and oxide layers. The metal layers of the first stacked structure are connected to the semiconductor layers of the second stacked structure.

公开(公告)号：US09583536B2

公开(公告)日：2017-02-28

申请号：US14806832

申请日：2015-07-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Chao-I Wu ,  Yu-Hsuan Lin ,  Dai-Ying Lee

IPC: H01L47/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2409 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1633 ,  H01L45/1641 ,  H01L45/1691

Abstract: A memory device having an array area and a periphery area is provided. The memory device includes a substrate, an isolation layer formed in the substrate, a first doped region formed on the isolation layer in the array area, a second doped region formed on the first doped region, a metal silicide layer formed on the second doped region, and a metal silicide oxide layer formed on the metal silicide layer.

Abstract translation: 提供具有阵列区域和周边区域的存储器件。 存储器件包括衬底，形成在衬底中的隔离层，形成在阵列区域中的隔离层上的第一掺杂区域，形成在第一掺杂区域上的第二掺杂区域，形成在第二掺杂区域上的金属硅化物层 以及形成在金属硅化物层上的金属硅化物层。

公开(公告)号：US20170025473A1

公开(公告)日：2017-01-26

申请号：US14806832

申请日：2015-07-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Chao-I Wu ,  Yu-Hsuan Lin ,  Dai-Ying Lee

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2409 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1633 ,  H01L45/1641 ,  H01L45/1691

Abstract: A memory device having an array area and a periphery area is provided. The memory device includes a substrate, an isolation layer formed in the substrate, a first doped region formed on the isolation layer in the array area, a second doped region formed on the first doped region, a metal silicide layer formed on the second doped region, and a metal silicide oxide layer formed on the metal silicide layer.

Abstract translation: 提供具有阵列区域和周边区域的存储器件。 存储器件包括衬底，形成在衬底中的隔离层，形成在阵列区域中的隔离层上的第一掺杂区域，形成在第一掺杂区域上的第二掺杂区域，形成在第二掺杂区域上的金属硅化物层 以及形成在金属硅化物层上的金属硅化物层。

公开(公告)号：US09455270B1

公开(公告)日：2016-09-27

申请号：US14831932

申请日：2015-08-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai

IPC: H01L27/115 ,  H01L21/768 ,  H01L21/308 ,  H01L23/535

CPC classification number: H01L27/11582 ,  H01L21/0271 ,  H01L21/0337 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate having a trench, a stacked structure, an etching stop structure, a plurality of memory structure, and a first filled slit groove formed in the stacked structure. The stacked structure has a horizontal extended region and a vertical extended region extending along a sidewall of the trench. The stacked structure includes a plurality of conductive layer s and a plurality of insulating layers interlacedly stacked in the trench. The etching stop structure is formed in the vertical extended region. The memory structures vertically penetrate through the conductive layers and the insulating layers in the horizontal extended region. The conductive layers and the insulating layers in the vertical extended region are formed on the etching stop structure and located between the etching stop structure and the first filled slit groove.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括具有沟槽的衬底，层叠结构，蚀刻停止结构，多个存储结构和形成在堆叠结构中的第一填充狭缝槽。 堆叠结构具有沿着沟槽的侧壁延伸的水平延伸区域和垂直延伸区域。 堆叠结构包括多个导电层和交错堆叠在沟槽中的多个绝缘层。 蚀刻停止结构形成在垂直延伸区域中。 存储器结构垂直地穿过导电层和水平延伸区域中的绝缘层。 垂直延伸区域中的导电层和绝缘层形成在蚀刻停止结构上并且位于蚀刻停止结构和第一填充狭缝槽之间。

公开(公告)号：US20160247814A1

公开(公告)日：2016-08-25

申请号：US14730340

申请日：2015-06-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Kuang-Hao Chiang

IPC: H01L27/115 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/31144 ,  H01L21/764 ,  H01L29/4234

Abstract: A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. Two stacked structures are formed a substrate. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers and a top insulating layer. A charge trapping structure and a channel layer are formed. The charge trapping structure includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched and part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the first dielectric layers and the second dielectric layers to connect the channel layer.

Abstract translation: 提供半导体器件及其半导体器件的制造方法。 该制造方法包括以下步骤。 两个堆叠结构形成基板。 每个堆叠结构包括多个栅极层，多个栅极绝缘层和顶部绝缘层。 形成电荷捕获结构和沟道层。 电荷捕获结构包括多个第一电介质层和多个第二电介质层。 蚀刻每个第一电介质层的一部分，蚀刻每个第二电介质层的一部分以暴露沟道层的一部分。 在第一电介质层和第二电介质层上形成着接垫层以连接沟道层。

公开(公告)号：US20160247813A1

公开(公告)日：2016-08-25

申请号：US14629537

申请日：2015-02-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai

IPC: H01L27/115 ,  H01L21/311 ,  H01L29/04 ,  H01L29/49 ,  H01L29/16 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L29/04 ,  H01L29/16 ,  H01L29/4234 ,  H01L29/4916

Abstract: A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. A bottom insulating layer is formed on a substrate. Two stacked structures are formed on the bottom insulating layer. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers, a top insulating layer and a conductive mask layer. Each of the charge trapping structures includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched. Part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the conductive mask layer, the first dielectric layers and the second dielectric layers to connect the conductive mask layer and the channel layer.

Abstract translation: 提供半导体器件及其半导体器件的制造方法。 该制造方法包括以下步骤。 底部绝缘层形成在基板上。 在底部绝缘层上形成两个堆叠结构。 每个堆叠结构包括多个栅极层，多个栅极绝缘层，顶部绝缘层和导电掩模层。 每个电荷俘获结构包括多个第一电介质层和多个第二电介质层。 每个第一介电层的一部分被蚀刻。 每个第二电介质层的一部分被蚀刻以暴露沟道层的一部分。 在导电掩模层，第一介电层和第二介电层上形成着衬垫层，以连接导电掩模层和沟道层。

公开(公告)号：US20160240551A1

公开(公告)日：2016-08-18

申请号：US14620281

申请日：2015-02-12

Applicant: MACRONIX INTERNATIONAL CO., LTD

Inventor： Erh-Kun Lai

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, stacks, a blocking layer-trapping layer-tunneling layer structure, channel layers, a first insulating material and a dielectric layer. The stacks are formed on the substrate. Each stack comprises a group of alternating conductive strips and insulating strips as well as a first string select line formed on the group. The blocking layer-trapping layer-tunneling layer structure and the channel layers are formed conformally with the stacks. The first insulating material is formed between the stacks and covers portions of the channel layers. The dielectric layer is formed on portions of the channel layers that are not covered by the first insulating material. The semiconductor structure further comprises second string select lines formed between the stacks on the first insulating material, wherein the second string select lines are separated from the channel layers by the dielectric layer.

Abstract translation: 提供半导体结构。 半导体结构包括衬底，堆叠，阻挡层 - 俘获层 - 隧道层结构，沟道层，第一绝缘材料和介电层。 堆叠形成在基板上。 每个堆叠包括一组交替的导电条和绝缘条以及形成在该组上的第一串选择线。 阻挡层 - 俘获层 - 隧道层结构和沟道层与堆叠共形地形成。 第一绝缘材料形成在堆叠之间并覆盖沟道层的部分。 介电层形成在通道层的未被第一绝缘材料覆盖的部分上。 半导体结构还包括形成在第一绝缘材料上的叠层之间的第二串选择线，其中第二串选择线通过电介质层与沟道层分离。

公开(公告)号：US09379131B2

公开(公告)日：2016-06-28

申请号：US14506791

申请日：2014-10-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai

IPC: H01L27/115 ,  H01L23/528 ,  G11C16/04 ,  G11C16/34 ,  H01L29/66

CPC classification number: H01L27/11582 ,  G11C16/0466 ,  G11C16/3418 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/66833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D stacked semiconductor structure is provided, comprising a plurality of multi-layered pillars formed on a substrate and spaced apart from each other, a plurality of first conductors formed between the adjacent multi-layered pillars, a plurality of charging-trapping layers formed on the substrate and on the sidewalls of the multi-layered pillars for separating the first conductor and the multi-layered pillars, and a second conductor formed on the first conductors and on the charging-trapping layers. One of the multi-layered pillars comprises a plurality of insulating layers and a plurality of conductive layers arranged alternately. The top surfaces of the first conductors are higher than the top surfaces of the multi-layered pillars so as to create a plurality of receiving trenches respectively on the multi-layered pillars. The second conductor fills up the receiving trenches on the multi-layered pillars.

Abstract translation: 提供了一种3D堆叠半导体结构，包括形成在基板上并彼此间隔开的多个多层柱，形成在相邻的多层柱之间的多个第一导体，多个充电陷阱层，形成在 所述基板和用于分离所述第一导体和所述多层支柱的所述多层支柱的侧壁上，以及形成在所述第一导体上和所述充电捕获层上的第二导体。 多层支柱之一包括交替布置的多个绝缘层和多个导电层。 第一导体的顶表面高于多层支柱的顶表面，以便在多层支柱上分别形成多个接收沟槽。 第二导体填充多层支柱上的接收沟槽。

公开(公告)号：US20160064404A1

公开(公告)日：2016-03-03

申请号：US14474399

申请日：2014-09-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a stack of alternate conductive layers and insulating layers, an opening, an oxide layer and a conductor. The stack is formed on the substrate. The opening penetrates through the stack. The oxide layer is formed on a sidewall of the opening. The conductor is filled into the opening. The conductor is separated from the sidewall of the opening by only the oxide layer.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括衬底，交替导电层和绝缘层的堆叠，开口，氧化物层和导体。 堆叠形成在基板上。 开口穿过堆叠。 氧化物层形成在开口的侧壁上。 导体填充到开口中。 导体仅通过氧化物层与开口的侧壁分离。