公开(公告)号：US08288225B2

公开(公告)日：2012-10-16

申请号：US13010563

申请日：2011-01-20

申请人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

发明人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.

摘要翻译： 非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。 相邻的串由浅沟槽隔离结构隔离。

公开(公告)号：US07910434B2

公开(公告)日：2011-03-22

申请号：US12567257

申请日：2009-09-25

申请人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

发明人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.

摘要翻译： 非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。 相邻的串由浅沟槽隔离结构隔离。

公开(公告)号：US07795080B2

公开(公告)日：2010-09-14

申请号：US12014689

申请日：2008-01-15

申请人： Takashi Orimoto ,  George Matamis ,  James Kai ,  Tuan Pham ,  Masaaki Higashitani ,  Henry Chien

发明人： Takashi Orimoto ,  George Matamis ,  James Kai ,  Tuan Pham ,  Masaaki Higashitani ,  Henry Chien

IPC分类号： H01L21/82

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521

摘要： Methods of fabricating integrated circuit devices are provided using composite spacer formation processes. A composite spacer structure is used to pattern and etch the layer stack when forming select features of the devices. A composite storage structure includes a first spacer formed from a first layer of spacer material and second and third spacers formed from a second layer of spacer material. The process is suitable for making devices with line and space sizes at less then the minimum resolvable feature size of the photolithographic processes being used. Moreover, equal line and space sizes at less than the minimum feature size are possible. In one embodiment, an array of dual control gate non-volatile flash memory storage elements is formed using composite spacer structures. When forming the active areas of the substrate, with overlying strips of a layer stack and isolation regions therebetween, a composite spacer structure facilitates equal lengths of the strips and isolation regions therebetween.

摘要翻译： 使用复合间隔物形成工艺提供制造集成电路器件的方法。 当形成设备的选择特征时，使用复合间隔物结构来图案化和蚀刻层堆叠。 复合存储结构包括由第一隔离物材料层形成的第一间隔物和由第二隔离物材料层形成的第二和第三间隔物。 该方法适用于制造具有小于所使用的光刻工艺的最小可分辨特征尺寸的线和空间尺寸的装置。 此外，等于线和空间尺寸小于最小特征尺寸是可能的。 在一个实施例中，使用复合间隔结构形成双控制非易失性闪存存储元件阵列。 当形成衬底的活性区域时，具有叠层的叠层和隔离区之间的复合间隔结构有利于条之间的等长长度和隔离区。

公开(公告)号：US20080248622A1

公开(公告)日：2008-10-09

申请号：US12061641

申请日：2008-04-02

申请人： George Matamis ,  Takashi Orimoto ,  Masaaki Higashitani ,  James Kai ,  Tuan Pham

发明人： George Matamis ,  Takashi Orimoto ,  Masaaki Higashitani ,  James Kai ,  Tuan Pham

IPC分类号： H01L21/336

CPC分类号： H01L27/11543 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11541

摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated peripheral circuitry formation are provided. Strips of charge storage material elongated in a row direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. Forming the strips defines the dimension of the resulting charge storage structures in the column direction. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. Strips of control gate material are formed between strips of charge storage material adjacent in the column direction. The strips of charge storage and control gate material are divided along their lengths in the row direction as part of forming isolation trenches and columns of active areas. After dividing the strips, the charge storage material at the peripheral circuitry region of the substrate is etched to define a gate dimension in the column direction for a peripheral transistor. Control gate interconnects can be formed to connect together rows of isolated control gates to extrinsically form word lines.

摘要翻译： 提供了具有双控制栅极存储器单元的非易失性半导体存储器件及其使用集成的外围电路形成形成其的方法。 形成沿着行方向延伸穿过衬底表面的电荷存储材料带，其间具有隧道介电材料带。 形成条带限定了所得电荷存储结构在列方向上的尺寸。 在一个实施例中，电荷存储材料条可以包括多层电荷存储材料以形成复合电荷存储结构。 控制栅极材料条形成在沿着列方向相邻的电荷存储材料的条带之间。 电荷存储和控制栅极材料条沿着它们在行方向上的长度被划分，作为形成隔离沟槽和有源区的列的一部分。 在分割条之后，蚀刻衬底的外围电路区域处的电荷存储材料，以便在外围晶体管的列方向上限定栅极尺寸。 可以形成控制栅极互连以将行隔离的控制栅极连接在一起，以外部地形成字线。

公开(公告)号：US20080076217A1

公开(公告)日：2008-03-27

申请号：US11534135

申请日：2006-09-21

申请人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

发明人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.

摘要翻译： 非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。 相邻的串由浅沟槽隔离结构隔离。 具有倒T形浮置栅极的阵列可以以自对准的方式形成。

公开(公告)号：US20070147118A1

公开(公告)日：2007-06-28

申请号：US11319260

申请日：2005-12-27

申请人： Tuan Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Hemink

发明人： Tuan Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Hemink

IPC分类号： G11C16/04 ,  G11C11/34 ,  G11C16/06

CPC分类号： G11C16/0483 ,  H01L23/5222 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534 ,  H01L2924/0002 ,  H01L2924/00

摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.

摘要翻译： NAND闪存器件采用独特的增压板设计。 升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。 升压板还屏蔽浮动栅极之间的不必要的耦合。 自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。 因此，根据本发明可以实现更紧凑和可靠的存储器件。

公开(公告)号：US08951859B2

公开(公告)日：2015-02-10

申请号：US13301560

申请日：2011-11-21

申请人： Masaaki Higashitani ,  Peter Rabkin

发明人： Masaaki Higashitani ,  Peter Rabkin

IPC分类号： H01L21/8239 ,  H01L29/792 ,  H01L49/02 ,  H01L27/115

CPC分类号： H01L29/7926 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L28/20 ,  H01L28/87 ,  H01L28/88

摘要： A method for fabricating passive devices such as resistors and capacitors for a 3D non-volatile memory device. In a peripheral area of a substrate, alternating layers of a dielectric such as oxide and a conductive material such as heavily doped polysilicon or metal silicide are provided in a stack. The substrate includes one or more lower metal layers connected to circuitry. One or more upper metal layers are formed above the stack. Contact structures are formed which extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel or serially by the contact structures and the at least one upper metal layer. Additional contact structures can connect the circuitry to the one or more upper metal layers. The passive device can be fabricated concurrently with a 3D memory array using common processing steps.

摘要翻译： 一种用于制造用于3D非易失性存储器件的诸如电阻器和电容器的无源器件的方法。 在衬底的外围区域中，叠层中提供诸如氧化物和诸如重掺杂多晶硅或金属硅化物的导电材料的电介质的交替层。 衬底包括连接到电路的一个或多个下部金属层。 在堆叠上方形成一个或多个上金属层。 形成了从导电材料层延伸到一个或多个上金属层的部分的接触结构，使得导电材料层彼此平行或连续地由接触结构和至少一个上金属层 。 附加接触结构可以将电路连接到一个或多个上金属层。 可以使用常规的处理步骤与3D存储器阵列同时地制造无源器件。

公开(公告)号：US08933502B2

公开(公告)日：2015-01-13

申请号：US13301597

申请日：2011-11-21

申请人： Masaaki Higashitani ,  Peter Rabkin

发明人： Masaaki Higashitani ,  Peter Rabkin

IPC分类号： H01L27/06 ,  G11C16/06 ,  H01L27/115 ,  G11C16/04

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  G11C16/06 ,  H01L23/53209 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/4916 ,  H01L2924/0002 ,  H01L2924/00

摘要： A stacked non-volatile memory cell array include cell areas with rows of vertical columns of NAND cells, and an interconnect area, e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect extending between insulation-filled slits, and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays.

摘要翻译： 堆叠的非易失性存储单元阵列包括具有NAND单元的垂直列行的单元区域，以及例如阵列中途并且延伸阵列的长度的互连区域。 互连区域包括在绝缘填充的狭缝之间延伸的至少一个金属硅化物互连，并且不包括NAND单元的垂直列。 金属硅化物互连可以将电力和控制信号从堆叠下方传递到堆叠之上。 金属硅化物互连也可以形成在衬底的周边区域中。 接触结构可以从互连的梯形部分延伸到堆叠之上的至少一个上金属层，以完成从堆叠下方的电路到上金属层的导电路径。 可以在阵列的平面中提供子阵列，而不需要字线连接和子阵列之间的传输区域。

公开(公告)号：US20130314995A1

公开(公告)日：2013-11-28

申请号：US13479649

申请日：2012-05-24

申请人： Deepanshu Dutta ,  Mohan Dunga ,  Masaaki Higashitani

发明人： Deepanshu Dutta ,  Mohan Dunga ,  Masaaki Higashitani

IPC分类号： G11C16/14 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C7/1006 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16

摘要： A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping in the substrate.

摘要翻译： 一种用于擦除诸如包括非用户数据或虚拟存储元件的NAND串的非易失性存储器的技术。 非用户数据存储元件的电压通过施加到衬底的擦除电压的受控增加而被电容性耦合。 通过使通路栅极晶体管处于非导通状态来浮置电压，其中通过栅极晶体管位于电压驱动器和非用户数据存储元件之间。 选择栅极晶体管的电压也可以电容耦合得更高。 衬底电压可以逐步增加和/或作为连续斜坡增加。 在一种方法中，外部虚拟存储元件浮动，同时内部虚拟存储元件被驱动。 在另一种方法中，外部和内部虚拟存储元件都浮起来。 由于基板中的电荷捕获减少，存储元件的写擦除耐久性增加。

公开(公告)号：US08450174B2

公开(公告)日：2013-05-28

申请号：US13173537

申请日：2011-06-30

申请人： Masaaki Higashitani

发明人： Masaaki Higashitani

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/743 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well.

摘要翻译： 公开了一种非易失性存储装置，其包括形成在阱上的一组连接的非易失性存储元件，位于阱中的位线触点，位于阱中的源极线接触件，连接到该阱的位线 位线接触，以及连接到源极线接触点和阱的源极线。