公开(公告)号：US06643208B2

公开(公告)日：2003-11-04

申请号：US10347220

申请日：2003-01-21

申请人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

发明人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： G11C00700

CPC分类号： G11C5/14 ,  G11C5/147 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4074 ,  H03K19/0016

摘要： A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in access with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

摘要翻译： 分别提供电压VCL1和VSL1的可变阻抗电源线和可变阻抗接地线在待机周期和行相关信号设定周期中被设置为低阻抗状态，并且在 列电路有效时间段。 可变阻抗电源线和可变阻抗地线供电电压VCL2和VSL2分别在待机周期中被设置为高阻抗状态，并且在有效周期和行相关信号复位时间段中被设置为低阻抗状态。 变频器作为工作电源电压VCL1和VSL2或电压VCL2和VSL1，在待机周期和激活循环中的输出信号的逻辑电平进行访问。 因此，提供半导体存储器件，其中可以减少备用循环中的次阈值电流和有效周期中的有效直流电流。

公开(公告)号：US06404056B1

公开(公告)日：2002-06-11

申请号：US09313249

申请日：1999-05-18

申请人： Shigehiro Kuge ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

发明人： Shigehiro Kuge ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC分类号： H01L2940

CPC分类号： H01L23/5286 ,  H01L27/0207 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： On transistors P1, P2, N1 and N2 constituting an NAND gate, a interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the interconnection pattern W of metal having high melting point, signal lines SL and SL′ for signal input/output between the NAND gate and the outside are formed by aluminum interconnection pattern Al1, and power supply lines VL and VL′ for applying power supply potentials Vcc and Vss to the NAND gate are formed by the aluminum interconnection pattern Al2. As compared with the prior art in which the local line LL is formed by the aluminum interconnection pattern Al1, the degree of freedom in layout can be improved and the layout area can be reduced.

摘要翻译： 在构成NAND门的晶体管P1，P2，N1，N2上，堆叠具有高熔点金属的互连图案W和铝互连图案Al1和Al2。 用于将晶体管P1，P2，N1和N2相互连接的本地线路LL通过具有高熔点金属的互连图案W，在与非门与外部之间的信号输入/输出的信号线SL和SL'形成 由铝互连图案Al1形成，并且用于将电源电位Vcc和Vss施加到NAND门的电源线VL和VL'由铝互连图案Al2形成。 与通过铝互连图案Al1形成局部线LL的现有技术相比，可以提高布局的自由度，并且可以减小布局面积。

公开(公告)号：US06246625B1

公开(公告)日：2001-06-12

申请号：US09497199

申请日：2000-02-03

申请人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

发明人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C5/14 ,  G11C5/147 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4074 ,  H03K19/0016

摘要： A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

摘要翻译： 分别提供电压VCL1和VSL1的可变阻抗电源线和可变阻抗接地线在待机周期和行相关信号设定周期中被设置为低阻抗状态，并且在 列电路有效时间段。 可变阻抗电源线和可变阻抗地线供电电压VCL2和VSL2分别在待机周期中被设置为高阻抗状态，并且在有效周期和行相关信号复位时间段中被设置为低阻抗状态。 根据待机周期和激活周期中的输出信号的逻辑电平，变频器作为电压VCL1和VSL2的工作电源电压或电压VCL2和VSL1运行。 因此，提供半导体存储器件，其中可以减少备用循环中的次阈值电流和有效周期中的有效直流电流。

公开(公告)号：US06194776B1

公开(公告)日：2001-02-27

申请号：US08850111

申请日：1997-05-01

申请人： Teruhiko Amano ,  Masaki Tsukude

发明人： Teruhiko Amano ,  Masaki Tsukude

IPC分类号： H01L2900

CPC分类号： H01L21/823493 ,  H01L21/761 ,  H01L29/1079 ,  H01L29/1087 ,  Y10S257/901

摘要： A semiconductor circuit device having a triple-well structure wherein a predetermined potential level is supplied to a top well without a contact region formed in the top well is disclosed. In an N-type ion implantation step for forming an N-type well region (1) in a P-type semiconductor substrate (5), a mask of a predetermined configuration is used so that ions are not implanted into a region of a portion which is to serve as a bottom portion (1B) of the well region (1). Then, the N-type well region (1) is formed which is shaped such that a portion (6) having P-type properties remains partially in the bottom portion (1B). The P-type portion (6) establishes electrical connection between a P-type well region (2) and the semiconductor substrate (5) to permit the potential applied to a contact region (4) to be supplied to the well region (2) therethrough. The portion (6) may include a plurality of portions (6) which allow uniform potential supply. This structure may be applied to basic cells of a memory cell array block.

摘要翻译： 公开了一种具有三阱结构的半导体电路器件，其中将预定电位电平提供给顶部阱，而不形成在顶部阱中的接触区域。 在用于在P型半导体衬底（5）中形成N型阱区（1）的N型离子注入步骤中，使用预定构造的掩模，使得离子不被注入到部分的区域中 其用作井区（1）的底部（1B）。 然后，形成N型阱区域（1），其形状使得具有P型特性的部分（6）部分地保留在底部（1B）中。 P型部分（6）建立P型阱区（2）和半导体衬底（5）之间的电连接，以允许施加到接触区（4）的电势被提供给阱区（2） 通过。 部分（6）可以包括允许均匀电势供应的多个部分（6）。 该结构可以应用于存储单元阵列块的基本单元。

公开(公告)号：US5917765A

公开(公告)日：1999-06-29

申请号：US951591

申请日：1997-10-16

申请人： Fukashi Morishita ,  Masaki Tsukude

发明人： Fukashi Morishita ,  Masaki Tsukude

IPC分类号： G01R31/28 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C29/06 ,  G11C29/50 ,  H01L21/66 ,  G11C13/00

CPC分类号： G11C29/50008 ,  G11C29/028 ,  G11C29/50 ,  G11C5/147 ,  G11C11/401 ,  G11C2029/5004

摘要： A semiconductor integrated circuit device realizing high speed operation and low current consumption and ensure reliability evaluation is provided. Reference voltage generating circuits for generating reference voltages of mutually different voltage levels are provided for power supply pads respectively, and voltage down converters for down converting power supply voltages of corresponding external power supply pads to corresponding reference voltage levels and transmitting the lowered voltages to corresponding internal power supply lines are provided corresponding to respective reference voltage generating circuits. Further, a switching transistor is provided at an output node of the reference voltage generating circuit which is rendered conductive at a stress acceleration mode for connecting the corresponding external power supply pad to the output node of the corresponding reference voltage generating circuit.

摘要翻译： 提供实现高速运行和低电流消耗并确保可靠性评估的半导体集成电路装置。 提供用于产生相互不同电压电平的参考电压的参考电压产生电路，以及用于将相应的外部电源焊盘的电源电压下变换为相应的参考电压电平的降压转换器，并将降低的电压传输到相应的内部 对应于各个参考电压产生电路提供电源线。 此外，开关晶体管设置在基准电压产生电路的输出节点处，其以应力加速模式导通，用于将相应的外部电源焊盘连接到相应的参考电压产生电路的输出节点。

公开(公告)号：US5894440A

公开(公告)日：1999-04-13

申请号：US189276

申请日：1994-01-31

申请人： Masaki Tsukude ,  Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi

发明人： Masaki Tsukude ,  Kazutami Arimoto ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Tsukasa Ooishi

IPC分类号： G11C11/401 ,  G11C7/06 ,  G11C7/10 ,  G11C11/409

CPC分类号： G11C7/06 ,  G11C7/1006 ,  G11C7/1039

摘要： Each of divided bit line pairs is selectively connected to a sub-input/output line pair through transfer gates. A register is connected to the sub-input/output line pair. Data is transferred through the sub-input/output line pair between the register and a selected bit line pair. A sense amplifier is connected to each of the bit line pairs. Sense amplifiers are independently driven by separate sense amplifier activating signals. Therefore, even if data is transferred to the selected bit line pair from the register, fluctuations in potential on the bit line pair caused in such a case does not affect a sense amplifier activating signal connected to a non-selected bit line pair. As a result, data stored in the non-selected memory cell is prevented from being destroyed.

摘要翻译： 每个分开的位线对通过传输门选择性地连接到子输入/输出线对。 寄存器连接到子输入/输出线对。 数据通过寄存器和所选位线对之间的子输入/输出线对传输。 读出放大器连接到每个位线对。 感测放大器由独立的读出放大器激活信号驱动。 因此，即使数据从寄存器传送到所选择的位线对，在这种情况下引起的位线对上的电位波动也不影响连接到未选位线对的读出放大器激活信号。 结果，防止存储在未选择的存储单元中的数据被破坏。

公开(公告)号：USRE36027E

公开(公告)日：1999-01-05

申请号：US664081

申请日：1996-06-13

申请人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Masaki Tsukude ,  Tsukasa Ohishi

发明人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Masaki Tsukude ,  Tsukasa Ohishi

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/41 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/1048

摘要： In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of V.sub.CC -V.sub.th, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of 1/2.multidot.V.sub.CC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.

摘要翻译： 在CSL系统的动态RAM中，存储器阵列被分成多个存储器阵列部分，并且设置在各个存储器阵列部分中的位线对响应于CSL输出而同时连接到它们对应的I / O线对 。 在这样的RAM中，只有要访问的存储器阵列部分的I / O线对被预充电到VCC-Vth的电平，而不存储阵列部分的I / O线对被预充电到 + E，fra 1/2 + EE xVCC的电平与位线对相同。 这使得可以实现更快的数据读取操作，并且还防止不必要的电流在未加工的存储器阵列部分中的位线对和I / O线对之间流动。

公开(公告)号：US5856951A

公开(公告)日：1999-01-05

申请号：US864756

申请日：1997-05-29

申请人： Kazutami Arimoto ,  Masaki Tsukude

发明人： Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： G11C11/408 ,  G11C5/14 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/413 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H03K19/00 ,  G11C7/00

CPC分类号： G11C11/4074 ,  G11C5/14 ,  G11C5/147

摘要： In a semiconductor integrated circuit device, a voltage setting circuit for setting a voltage level on the sub power source voltage line according to a reference voltage from a reference voltage generating circuit, is provided between a main power source voltage line and a sub power source voltage line. While a current consumption at the standby cycle is reduced, increase of the access delay is prevented. The voltage setting circuit includes a differential amplifier for differentially amplifying a voltage on the sub power source line and the reference voltages and a transistor responsive to an output of the differential amplifier for causing a current flow between the main and sub power source lines, or alternatively a diode-connected insulated gate type transistor receiving the reference voltage at a back gate thereof.

摘要翻译： 在半导体集成电路装置中，在主电源电压线和副电源电压之间设置用于根据来自基准电压发生电路的基准电压设定副电源电压线上的电压电平的电压设定电路 线。 虽然在备用周期的电流消耗减少，但是阻止了访问延迟的增加。 电压设定电路包括用于差分放大副电源线上的电压和参考电压的差分放大器，以及响应于差分放大器的输出以在主电源线和副电源线之间引起电流的晶体管，或者 二极管连接的绝缘栅型晶体管，在其后栅极接收参考电压。

公开(公告)号：US5825705A

公开(公告)日：1998-10-20

申请号：US839834

申请日：1997-04-17

申请人： Masaki Tsukude ,  Kazutami Arimoto

发明人： Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： G11C11/403 ,  G11C5/14 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/402

CPC分类号： G11C11/4074 ,  G11C11/406 ,  G11C5/147

摘要： A timing generating circuit generates a signal SRE defining a period in which a self-refreshing operation is carried out based on a signal extRAS and a signal extCAS. An internal voltage down-converting circuit controls the level of an internal power supply voltage intVcc to be generated in the period defined by the signal SRE lower in the self-refreshing operation than in a normal operation. As a result, a semiconductor memory device is obtained which reduces current consumption in the self-refreshing operation by simple control in an internal circuit.

公开(公告)号：US5812490A

公开(公告)日：1998-09-22

申请号：US912200

申请日：1997-08-18

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1051

摘要： An external clock signal ext.CLK applied to an external clock input pad is transferred to two internal clock generation circuits independent from each other through two independent input first stage circuits. An internal clock signal int.CLK1 controlling the operations of row related circuits and column related circuits is supplied by a first clock generation circuit and an internal clock signal int.CLK2 controlling an output buffer circuit is supplied from a second clock generation circuit.

摘要翻译： 施加到外部时钟输入焊盘的外部时钟信号ext.CLK通过两个独立的输入第一级电路彼此独立地传送到两个内部时钟产生电路。 控制行相关电路和列相关电路的操作的内部时钟信号int.CLK1由第一时钟产生电路提供，并且控制输出缓冲器电路的内部时钟信号int.CLK2由第二时钟发生电路提供。