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44 条记录 (耗时 0.029 秒)

    Semiconductor integrated circuit device
    31.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20050201193A1

    公开(公告)日：2005-09-15

    申请号：US11074897

    申请日：2005-03-09

    申请人： Naoki Kuroda ,  Yuji Nakai

    发明人： Naoki Kuroda ,  Yuji Nakai

    IPC分类号： G06F12/00 ,  G06F12/04 ,  G11C7/00 ,  G11C8/00 ,  G11C11/4063

    CPC分类号： G11C7/10 ,  G11C7/1006 ,  G11C2207/107

    摘要： A plurality of logic circuits both access the DRAM block by way of an access circuit. The operation clock for the DRAM block is set at a higher frequency than the system clock for the logic circuits. Outputs of a first bit width from the logic circuits are subjected to serial/parallel conversion into data of a second bit width and the data is written into the DRAM block.

    摘要翻译： 多个逻辑电路都通过访问电路访问DRAM块。 DRAM块的操作时钟设置在比逻辑电路的系统时钟更高的频率上。 来自逻辑电路的第一位宽的输出经过串行/并行转换为第二位宽的数据，并将数据写入DRAM块。

    Semiconductor integrated circuit device
    32.
    发明申请
    Semiconductor integrated circuit device 审中-公开
    半导体集成电路器件

    公开(公告)号：US20050201142A1

    公开(公告)日：2005-09-15

    申请号：US11072298

    申请日：2005-03-07

    申请人： Naoki Kuroda

    发明人： Naoki Kuroda

    IPC分类号： G11C11/407 ,  G11C11/24

    CPC分类号： G11C5/147 ,  G11C11/4074

    摘要： A large capacity DRAM block, which is accessible by a logic circuit, includes a VBB/VPP power supply circuit. The other DRAM blocks accessible by a logic circuit share the VBB/VPP power supply circuit of the large capacity DRAM block as their VBB/VPP power supply circuit.

    摘要翻译： 可由逻辑电路访问的大容量DRAM块包括VBB / VPP电源电路。 由逻辑电路可访问的其他DRAM块可将大容量DRAM块的VBB / VPP电源电路作为其VBB / VPP电源电路共享。

    Semiconductor memory device
    33.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08164938B2

    公开(公告)日：2012-04-24

    申请号：US12942627

    申请日：2010-11-09

    申请人： Naoki Kuroda ,  Yoshinobu Yamagami

    发明人： Naoki Kuroda ,  Yoshinobu Yamagami

    IPC分类号： G11C5/06

    CPC分类号： G11C11/412 ,  G11C8/16

    摘要： A semiconductor memory device includes a first inverter and a second inverter each having an input and an output, the output of each of the first and second inverters being connected to the input of the other so that data is stored, a CMOS switch configured to connect the input of the first inverter and a write bit line, a read MOS transistor having a gate connected to the output of the first inverter, and a MOS switch configured to connect the read MOS transistor to a read bit line. The first and second inverters have different sizes and are connected to different source power supplies.

    摘要翻译： 半导体存储器件包括第一反相器和第二反相器，每个具有输入和输出，第一和第二反相器的每一个的输出连接到另一个的输入，以便存储数据; CMOS开关，被配置为连接 第一反相器的输入和写入位线，具有连接到第一反相器的输出的栅极的读取MOS晶体管和被配置为将读取的MOS晶体管连接到读取位线的MOS开关。 第一和第二逆变器具有不同的尺寸并连接到不同的源电源。

    SEMICONDUCTOR STORAGE DEVICE
    35.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 有权
    半导体存储设备

    公开(公告)号：US20090116318A1

    公开(公告)日：2009-05-07

    申请号：US12191011

    申请日：2008-08-13

    申请人： Naoki Kuroda

    发明人： Naoki Kuroda

    IPC分类号： G11C7/14 ,  G11C7/10 ,  G11C7/00

    CPC分类号： G11C11/4099 ,  G11C7/08 ,  G11C7/14 ,  G11C7/227

    摘要： In a semiconductor storage device, such as a dynamic random access memory (DRAM), in which dynamic data is amplified and read on a bit line, a data line sense amplifier/write buffer connected to a data line of a memory array and a data line sense amplifier control signal generating logic circuit connected to a dummy data line of a dummy memory array are provided. A sense amplifier is activated in accordance with an output signal of the logic circuit.

    摘要翻译： 在其中动态数据在位线上被放大和读取的诸如动态随机存取存储器（DRAM）的半导体存储装置中，连接到存储器阵列的数据线的数据线读出放大器/写入缓冲器和数据 提供连接到虚拟存储器阵列的虚拟数据线的线读出放大器控制信号产生逻辑电路。 读出放大器根据逻辑电路的输出信号而被激活。

    Semiconductor integrated circuit
    36.
    发明申请
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US20080169950A1

    公开(公告)日：2008-07-17

    申请号：US11790737

    申请日：2007-04-27

    申请人： Naoki Yamada ,  Naoki Kuroda

    发明人： Naoki Yamada ,  Naoki Kuroda

    IPC分类号： H03M1/10 ,  H03M1/12

    CPC分类号： H03M1/1071

    摘要： The semiconductor integrated circuit includes: a plurality of macro cells; and a serial-parallel conversion circuit for converting a serial signal inputted from outside to generate parallel selection control signals during testing, or an A/D conversion circuit for converting an analog signal inputted from outside to generate digital selection control signals during testing. One or more among, the plurality of macro cells are selected based on the selection control signals and brought to a test operation state.

    摘要翻译： 半导体集成电路包括：多个宏小区; 以及用于转换从外部输入的串行信号以在测试期间产生并行选择控制信号的串并转换电路，或用于转换从外部输入的模拟信号以在测试期间产生数字选择控制信号的A / D转换电路。 基于选择控制信号选择多个宏小区中的一个或多个，并进入测试操作状态。

    Semiconductor memory device
    38.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20070025171A1

    公开(公告)日：2007-02-01

    申请号：US11492176

    申请日：2006-07-25

    申请人： Naoki Kuroda

    发明人： Naoki Kuroda

    IPC分类号： G11C11/34

    CPC分类号： G11C8/10 ,  G11C17/10

    摘要： In a memory cell array, source lines are provided so that each of the source lines is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a ground potential and lower than a power supply potential are provided so as to correspond to the source lines, respectively. In an active period, the source bias control circuits perform potential control so that one or more of the source lines selected by row predecoders which are not connected to one of the memory cells which is to be read out are controlled to be in a state where the source bias potential is supplied.

    摘要翻译： 在存储单元阵列中，提供源极线，使得每个源极线连接到属于相邻两行的存储单元中的每一个，以及用于提供高于地的源极偏置电位的多个源极偏置控制电路 提供电位并且低于电源电位以分别对应于源极线。 在有源时段中，源极偏置控制电路进行电位控制，使得由行预解码器选择的一个或多个未连接到要读出的存储单元之一的源极线被控制为处于 提供源极偏置电位。

    Semiconductor memory device
    39.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20070019490A1

    公开(公告)日：2007-01-25

    申请号：US11491934

    申请日：2006-07-25

    申请人： Naoki Kuroda ,  Masanobu Hirose

    发明人： Naoki Kuroda ,  Masanobu Hirose

    IPC分类号： G11C11/34

    CPC分类号： G11C17/12 ,  G11C2207/2227

    摘要： In a memory cell array, source lines are provided so that each of the source line is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a ground potential and lower than a power supply potential are provided so as to correspond to the source lines, respectively. During a stand-by period, each of the source lines is controlled to be in a state where the source bias potential is supplied and, during an active period, one or more of the source lines which are not connected to one of the memory cells which is to be read out are controlled to be in a state where the source bias potential is supplied.

    摘要翻译： 在存储单元阵列中，提供源极线，使得源极线中的每一个连接到属于相邻两行的存储单元中的每一个，以及用于提供高于地的源极偏置电位的多个源极偏置控制电路 提供电位并且低于电源电位以分别对应于源极线。 在待机期间，每个源极线被控制为处于源极偏置电位被提供的状态，并且在有效周期期间，一个或多个不连接到存储器单元之一的源极线 被读取的数据被控制为处于提供源极偏置电位的状态。

    Semiconductor integrated circuit device
    40.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07102413B2

    公开(公告)日：2006-09-05

    申请号：US10726302

    申请日：2003-12-01

    申请人： Naoki Kuroda

    发明人： Naoki Kuroda

    IPC分类号： H03K17/62

    CPC分类号： G11C29/021 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/12005 ,  G11C2029/5004 ,  G11C2207/105

    摘要： A semiconductor integrated circuit device including a plurality of internal power supply generating circuits arranged on a single chip and a common monitor pad is provided. The internal power supply generating circuits are connected via respective switches to the common monitor pad, and the internal power supply generating circuits and the monitor pad are selectively connectable using the switches.

    摘要翻译： 提供了包括布置在单个芯片上的多个内部电源产生电路和公共监视器焊盘的半导体集成电路器件。 内部电源产生电路通过相应的开关连接到公共监视器焊盘，并且使用开关可以选择性地连接内部电源发生电路和监视器焊盘。