公开(公告)号：US06853217B2

公开(公告)日：2005-02-08

申请号：US10647280

申请日：2003-08-26

申请人： Kazuo Tanaka ,  Hiroyuki Mizuno ,  Rie Nishiyama ,  Manabu Miyamoto

发明人： Kazuo Tanaka ,  Hiroyuki Mizuno ,  Rie Nishiyama ,  Manabu Miyamoto

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H03K3/356 ,  H03K19/0175 ,  H03K19/0185

CPC分类号： H03K3/356113 ,  H01L2924/0002 ,  H03K3/356104 ,  H01L2924/00

摘要： In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

公开(公告)号：US06715025B2

公开(公告)日：2004-03-30

申请号：US10186891

申请日：2002-07-02

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takao Watanabe

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takao Watanabe

IPC分类号： G06F1300

CPC分类号： G06F12/0607 ,  G06F12/0882

摘要： In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache contents. Accordingly, high speed accessing requires efficient assignment of the two kinds of accesses to banks of the DRAM. In assigning request addresses from the CPU to different banks of the DRAM, bank addresses of the DRAM are generated by operation of the INDEX field and the TAG field so that local accesses whose INDEX varies and accesses at the time of writing back of which INDEX remains the same but TAG differs can be assigned to different banks, thereby enabling high speed accessing. Furthermore, as reading and writing at the time of writing back can be assigned to a separate bank, pseudo dual-port accessing is made possible with only one port, resulting in higher speed write-back accessing.

摘要翻译： 在涉及由INDEX和TAG地址访问的高速缓冲存储器的信息处理装置中，对主存储器的访问包括归因于替代缓存内容的引用和回写访问的本地字符的许多访问。 因此，高速存取需要对DRAM的存储体的两种访问进行有效的分配。 在将请求地址从CPU分配给DRAM的不同库时，通过INDEX字段和TAG字段的操作来生成DRAM的存储区地址，以使其INDEX变化的本地访问在写入INDEX时被保留 相同但是TAG不同可以分配给不同的存储体，从而实现高速存取。 此外，由于在回写时的读写可以分配给单独的存储区，因此只能使用一个端口进行伪双端口访问，从而实现更高速的写回访问。

公开(公告)号：US06707334B2

公开(公告)日：2004-03-16

申请号：US10443018

申请日：2003-05-22

申请人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Takanori Shimura ,  Toshihiro Hattori

发明人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Takanori Shimura ,  Toshihiro Hattori

IPC分类号： H03K301

CPC分类号： H01L27/0207 ,  G11C5/14 ,  G11C5/146 ,  G11C5/147 ,  H01L27/0928 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/0016 ,  H01L2924/00

摘要： In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN1 and MP1) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.

摘要翻译： 为了提供满足快速操作和低功耗特性的诸如微处理器等的半导体IC单元，保持其高质量，本发明的半导体IC单元被构成为包括主电路（ LOG），其形成在半导体衬底上的晶体管和用于控制施加到衬底的电压的衬底偏置控制电路（VBC），并且主电路包括用于控制的开关晶体管（MN1和MP1） 将要施加到衬底的电压和从衬底偏置控制电路输出的控制信号输入到每个开关晶体管的栅极，并且控制信号返回到衬底偏置控制电路。

公开(公告)号：US06600360B2

公开(公告)日：2003-07-29

申请号：US10247525

申请日：2002-09-20

申请人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Takanori Shimura ,  Toshihiro Hattori

发明人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Takanori Shimura ,  Toshihiro Hattori

IPC分类号： H03K301

CPC分类号： H01L27/0207 ,  G11C5/14 ,  G11C5/146 ,  G11C5/147 ,  H01L27/0928 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/0016 ,  H01L2924/00

摘要： In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN1 and MP1) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.

公开(公告)号：US06535056B2

公开(公告)日：2003-03-18

申请号：US09874017

申请日：2001-06-06

申请人： Hiroyuki Mizuno

发明人： Hiroyuki Mizuno

IPC分类号： G05F110

CPC分类号： G06F1/324 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3296 ,  H03K19/0016 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20 ,  Y10T307/25 ,  Y10T307/406

摘要： A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.

公开(公告)号：US06515918B2

公开(公告)日：2003-02-04

申请号：US10067902

申请日：2002-02-08

申请人： Hiroyuki Mizuno ,  Takao Watanabe ,  Mitsuru Hiraki ,  Hitoshi Tanaka

发明人： Hiroyuki Mizuno ,  Takao Watanabe ,  Mitsuru Hiraki ,  Hitoshi Tanaka

IPC分类号： G11C700

CPC分类号： G11C5/14 ,  G11C5/147

摘要： A semiconductor device having a first circuit block supplied with a first operating voltage, a second circuit block supplied with a second operating voltage, a voltage generating circuit for generating a third operating voltage in response to the first operating voltage, and a third circuit block supplied with the third operating voltage. Preferably, the third operating voltage is generated such that the first operating voltage is increased to a fourth operating voltage by a voltage-up converter, and then the fourth operating voltage is dropped to the third operating voltage by a voltage down-converter. Hence, a power supply operating internally stably in spite of use of a relatively fluctuating voltage can be provided even in the case where a power-supply voltage is dropped.

公开(公告)号：US06510835B1

公开(公告)日：2003-01-28

申请号：US09889446

申请日：2001-08-20

申请人： Hiroyuki Mizuno ,  Noboru Takagi ,  Naohide Fuwa

发明人： Hiroyuki Mizuno ,  Noboru Takagi ,  Naohide Fuwa

IPC分类号： F02B1700

CPC分类号： F02D41/307 ,  F02B2075/125 ,  F02D41/123 ,  F02D41/1402 ,  F02D41/3029 ,  F02D2200/0402 ,  F02D2200/0404 ,  F02D2200/0406 ,  F02D2200/0414 ,  F02D2200/1004 ,  F02D2250/18 ,  F02D2250/24 ,  Y02T10/123 ,  Y02T10/128

摘要： An engine can switch a combustion mode between homogeneous charge combustion and stratified charge combustion. The engine is controlled in accordance with a load acting on the engine. When homogeneous charge combustion is executed, an intake pressure, or a parameter representing the amount of intake air, is used as a value representing an engine load. When stratified charge combustion is executed, a value equivalent to the intake pressure presuming homogeneous charge combustion is executed with the amount of manipulation of an acceleration pedal at that time is computed as a virtual intake pressure, and the virtual intake pressure is used as a value representing the engine load. In either combustion mode, therefore, the intake pressure, or a common parameter, is used as a value representing the engine load to control the engine. This simplifies matching of engine power torques between both combustion modes.

摘要翻译： 发动机可以在均质充气燃烧和分层充气燃烧之间切换燃烧模式。 发动机根据作用在发动机上的负载进行控制。 当执行均匀充气燃烧时，使用进气压力或表示进气量的参数作为表示发动机负荷的值。 当进行分层充气燃烧时，通过将该时刻的加速踏板的操纵量计算为虚拟进气压力，将虚拟进气压力用作值，执行与进行均匀充气燃烧时的进气压力相当的值 代表发动机负荷。 因此，在任一燃烧模式中，将进气压力或公共参数用作表示用于控制发动机的发动机负荷的值。 这简化了两种燃烧模式之间发动机功率转矩的匹配。

公开(公告)号：US06489824B2

公开(公告)日：2002-12-03

申请号：US09935717

申请日：2001-08-24

申请人： Masayuki Miyazaki ,  Koichiro Ishibashi ,  Takeshi Sakata ,  Satoru Hanzawa ,  Hiroyuki Mizuno ,  Kiyoshi Hasegawa ,  Masaru Kokubo ,  Hirokazu Aoki

发明人： Masayuki Miyazaki ,  Koichiro Ishibashi ,  Takeshi Sakata ,  Satoru Hanzawa ,  Hiroyuki Mizuno ,  Kiyoshi Hasegawa ,  Masaru Kokubo ,  Hirokazu Aoki

IPC分类号： H03L706

CPC分类号： H04L7/0008 ,  G06F1/10 ,  H03K5/135 ,  H04L7/0037

摘要： A timing-control circuit device, which uses a synchronous mirror delay circuit, for keeping the synchronization between clock signals in phase even at a load change. A reference clock signal (clkin 11) is entered to a timing-control circuit (SMDF 14) and used to generate an internal clock (dclk 12), then generates an external clock (clkout 13) through a buffer (BUF 15). The external clock signal is fed back to the timing-control circuit (SMDF 14) and used to generate an internal clock signal so as to synchronize the external clock signal in phase with the reference clock signal. The timing-control circuit is provided with a circuit (FDA 21, MCC 22) for detecting a phase difference between the internal clock signal and the external clock signal, as well as a delay circuit (DCL 24) for controlling a delay time, so that the delay circuit (DCL 24) can change the delay time according to the detected phase difference.

公开(公告)号：US06483374B1

公开(公告)日：2002-11-19

申请号：US09582485

申请日：2000-06-23

申请人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Takanori Shimura ,  Toshihiro Hattori

发明人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Takanori Shimura ,  Toshihiro Hattori

IPC分类号： H03K301

CPC分类号： H01L27/0207 ,  G11C5/14 ,  G11C5/146 ,  G11C5/147 ,  H01L27/0928 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/0016 ,  H01L2924/00

摘要： In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN1 and MP1) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.

公开(公告)号：US06469948B2

公开(公告)日：2002-10-22

申请号：US09885066

申请日：2001-06-21

申请人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

发明人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

IPC分类号： G11C800

CPC分类号： G11C11/406 ,  G11C7/1039 ,  G11C7/1072

摘要： A dynamic memory requires refreshing to retain data in its memory cells. This may cause access to the dynamic memory for purposes other than refreshing (external access) and access to it for refreshing to compete with each other, resulting in a performance deterioration. According to this invention, a pipelined dynamic memory. (PDRAM) is used, and the pipeline frequency (CLK) of the pipelined dynamic memory is made higher than the frequency (CLK1) of external access, and access required for refreshing is made to an unoccupied slot (a timing when any external access request is never issued) in the pipeline of the pipelined dynamic memory. This makes refreshing of the internal dynamic memory an internal operation, which eliminates the need to take refreshing into consideration at the time external access is made, leading to improvement in operating ease and speed.

摘要翻译： 动态存储器需要刷新以将数据保留在其存储单元中。 这可能导致访问动态存储器用于除了刷新（外部访问）之外的目的，并且访问它以进行刷新以相互竞争，导致性能恶化。 根据本发明，流水线动态存储器。 （PDRAM），并且使流水线动态存储器的流水线频率（CLK）高于外部访问的频率（CLK1），并且对未占用时隙进行刷新所需的访问（任何外部访问请求的定时 在流水线动态存储器的流水线中永远不会发布）。 这使得内部动态存储器的刷新成为内部操作，这消除了在外部访问时考虑到刷新的需要，从而改善了操作的容易性和速度。