公开(公告)号：US20120043599A1

公开(公告)日：2012-02-23

申请号：US12943349

申请日：2010-11-10

申请人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Ryouhei Kirisawa

发明人： Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Ryouhei Kirisawa

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first and a second stacked structure, a first and a second semiconductor pillar, a semiconductor connection portion, a first and a second connection portion conductive layer, a first and a second pillar portion memory layer, a first and a second connection portion memory layer. The first and second stacked structures include electrode films and inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is adjacent to the first stacked structure. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The semiconductor connection portion connects the first and second semiconductor pillars. The first and second pillar portion memory layers are provided between the electrode films and the semiconductor pillar. The first and second connection portion memory layers are provided between the connection portion conductive layers and the semiconductor connection portion.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一和第二堆叠结构，第一和第二半导体柱，半导体连接部分，第一和第二连接部分导电层，第一和第二柱部存储器 层，第一和第二连接部分存储层。 第一和第二堆叠结构包括在第一方向上交替堆叠的电极膜和电极间绝缘膜。 第二堆叠结构与第一堆叠结构相邻。 第一和第二半导体柱分别刺穿第一和第二堆叠结构。 半导体连接部分连接第一和第二半导体柱。 第一和第二柱部存储层设置在电极膜和半导体柱之间。 第一和第二连接部分存储层设置在连接部分导电层和半导体连接部分之间。

公开(公告)号：US20120132981A1

公开(公告)日：2012-05-31

申请号：US13112345

申请日：2011-05-20

申请人： Takeshi Imamura ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Ryouhei Kirisawa

发明人： Takeshi Imamura ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Ryouhei Kirisawa

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L27/11556 ,  H01L29/42324 ,  H01L29/7889

摘要： According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided.

摘要翻译： 根据一个实施例，提供了柱状半导体，通过隧道电介质膜形成在柱状半导体的侧表面上的浮栅电极和通过块状电介质膜包围浮置栅电极的控制栅电极。

公开(公告)号：US09025377B2

公开(公告)日：2015-05-05

申请号：US13052195

申请日：2011-03-21

申请人： Kunihiro Yamada ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Yoshiaki Fukuzumi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Kaori Kawasaki

发明人： Kunihiro Yamada ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Yoshiaki Fukuzumi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Kaori Kawasaki

IPC分类号： G11C16/22 ,  G11C16/04 ,  H01L27/115

CPC分类号： G11C16/0483 ,  G11C16/22 ,  H01L27/11578 ,  H01L27/11582

摘要： According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body. The channel body extends upward from a substrate to intersect a plurality of electrode layers stacked on the substrate. The method can include prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell.

摘要翻译： 根据一个实施例，公开了一种操作半导体存储器件的方法。 该方法可以包括将至少一个从通过主体连接的多个存储单元的最上层的存储单元和最下层的存储单元中选出的至少一个存储在只读数据中。 通道体从衬底向上延伸以与堆叠在衬底上的多个电极层交叉。 该方法可以包括禁止具有存储在只读存储器单元中的只读数据的只读存储器单元的数据擦除操作。

公开(公告)号：US08766351B2

公开(公告)日：2014-07-01

申请号：US13112345

申请日：2011-05-20

申请人： Takeshi Imamura ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Ryouhei Kirisawa

发明人： Takeshi Imamura ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Ryouhei Kirisawa

IPC分类号： H01L29/788

CPC分类号： H01L27/11556 ,  H01L29/42324 ,  H01L29/7889

摘要： According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided.

摘要翻译： 根据一个实施例，提供了柱状半导体，通过隧道电介质膜形成在柱状半导体的侧表面上的浮栅电极和通过块状电介质膜包围浮置栅电极的控制栅电极。

公开(公告)号：US08598643B2

公开(公告)日：2013-12-03

申请号：US13235425

申请日：2011-09-18

申请人： Kaori Kawasaki ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Takeshi Imamura ,  Ryouhei Kirisawa ,  Hideaki Aochi

发明人： Kaori Kawasaki ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Takeshi Imamura ,  Ryouhei Kirisawa ,  Hideaki Aochi

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一导电层，第二导电层，第一电极间绝缘膜和堆叠在第一导电层上方的第三导电层，存储膜，半导体层， 绝缘构件和硅化物层。 存储膜和半导体层形成在设置在第二导电层，第一电极间绝缘膜和第三导电层中的通孔的内表面上。 绝缘构件埋设在分割第二导电层，第一电极间绝缘膜和第三导电层的狭缝中。 硅化物层形成在狭缝中的第二导电层和第三导电层的表面上。 沿着狭缝的内表面，第二导电层和第三导电层之间的距离比层叠方向长。

公开(公告)号：US20120241846A1

公开(公告)日：2012-09-27

申请号：US13235425

申请日：2011-09-18

申请人： Kaori KAWASAKI ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Takeshi Imamura ,  Ryouhei Kirisawa ,  Hideaki Aochi

发明人： Kaori KAWASAKI ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Takeshi Imamura ,  Ryouhei Kirisawa ,  Hideaki Aochi

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一导电层，第二导电层，第一电极间绝缘膜和堆叠在第一导电层上方的第三导电层，存储膜，半导体层， 绝缘构件和硅化物层。 存储膜和半导体层形成在设置在第二导电层，第一电极间绝缘膜和第三导电层中的通孔的内表面上。 绝缘构件埋设在分割第二导电层，第一电极间绝缘膜和第三导电层的狭缝中。 硅化物层形成在狭缝中的第二导电层和第三导电层的表面上。 沿着狭缝的内表面，第二导电层和第三导电层之间的距离比层叠方向长。

公开(公告)号：US20120026775A1

公开(公告)日：2012-02-02

申请号：US13052195

申请日：2011-03-21

申请人： Kunihiro Yamada ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Yoshiaki Fukuzumi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Kaori Kawasaki

发明人： Kunihiro Yamada ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Yoshiaki Fukuzumi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Kaori Kawasaki

IPC分类号： G11C17/12

CPC分类号： G11C16/0483 ,  G11C16/22 ,  H01L27/11578 ,  H01L27/11582

摘要： According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body. The channel body extends upward from a substrate to intersect a plurality of electrode layers stacked on the substrate. The method can include prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell.

摘要翻译： 根据一个实施例，公开了一种操作半导体存储器件的方法。 该方法可以包括将至少一个从通过主体连接的多个存储单元的最上层的存储单元和最下层的存储单元中选出的至少一个存储在只读数据中。 通道体从衬底向上延伸以与堆叠在衬底上的多个电极层交叉。 该方法可以包括禁止具有存储在只读存储器单元中的只读数据的只读存储器单元的数据擦除操作。

公开(公告)号：US20110051527A1

公开(公告)日：2011-03-03

申请号：US12725827

申请日：2010-03-17

申请人： Ryouhei Kirisawa ,  Masaru Kito ,  Shigeto Oota ,  Yoshimasa Mikajiri

发明人： Ryouhei Kirisawa ,  Masaru Kito ,  Shigeto Oota ,  Yoshimasa Mikajiri

IPC分类号： G11C16/04 ,  G11C16/02

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected cell transistor of the first memory transistors, the control unit applies V1 voltage to the first wiring, applies V2 voltage lower than V1 to a selected cell gate of the selected cell transistor, applies V3 voltage not higher than V1 and higher than V2 to a non-selected cell gate of the first memory transistors, applies V1 or V4 voltage not higher than V1 and not lower than V3 to the first select gate, and applies V2 or V4 voltage higher than V2 and not higher than V3 to the second wiring or sets the second wiring in a floating state.

摘要翻译： 非易失性半导体存储器件包括：存储器单元; 和控制单元。 存储单元包括：第一和第二存储器串，分别包括具有第一和第二选择栅极的第一和第二存储器晶体管; 以及与其连接的第一和第二布线。 在第一存储晶体管的所选单元晶体管的选择性擦除操作中，控制单元向第一布线施加V1电压，向所选单元晶体管的选定单元栅极施加低于V1的V2电压，施加不高于 V1并且高于V2到第一存储晶体管的未选择的单元栅极，向第一选择栅施加不高于V1且不低于V3的V1或V4电压，并且施加V2或V4电压高于V2而不是更高 而不是V3到第二布线，或将第二布线置于浮置状态。

公开(公告)号：US08320182B2

公开(公告)日：2012-11-27

申请号：US12725827

申请日：2010-03-17

申请人： Ryouhei Kirisawa ,  Masaru Kito ,  Shigeto Oota ,  Yoshimasa Mikajiri

发明人： Ryouhei Kirisawa ,  Masaru Kito ,  Shigeto Oota ,  Yoshimasa Mikajiri

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected cell transistor of the first memory transistors, the control unit applies V1 voltage to the first wiring, applies V2 voltage lower than V1 to a selected cell gate of the selected cell transistor, applies V3 voltage not higher than V1 and higher than V2 to a non-selected cell gate of the first memory transistors, applies V1 or V4 voltage not higher than V1 and not lower than V3 to the first select gate, and applies V2 or V4 voltage higher than V2 and not higher than V3 to the second wiring or sets the second wiring in a floating state.

摘要翻译： 非易失性半导体存储器件包括：存储器单元; 和控制单元。 存储单元包括：第一和第二存储器串，分别包括具有第一和第二选择栅极的第一和第二存储器晶体管; 以及与其连接的第一和第二布线。 在第一存储晶体管的所选单元晶体管的选择性擦除操作中，控制单元向第一布线施加V1电压，向所选单元晶体管的选定单元栅极施加低于V1的V2电压，施加不高于 V1并且高于V2到第一存储晶体管的未选择的单元栅极，向第一选择栅施加不高于V1且不低于V3的V1或V4电压，并且施加V2或V4电压高于V2而不是更高 而不是V3到第二布线，或将第二布线置于浮置状态。

公开(公告)号：US08507972B2

公开(公告)日：2013-08-13

申请号：US12821551

申请日：2010-06-23

申请人： Shigeto Oota ,  Yoshimasa Mikajiri ,  Masaru Kito ,  Ryouhei Kirisawa

发明人： Shigeto Oota ,  Yoshimasa Mikajiri ,  Masaru Kito ,  Ryouhei Kirisawa

IPC分类号： H01L29/94

CPC分类号： H01L29/792 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structural unit, a semiconductor pillar, a memory layer, an inner insulating film, an outer insulating film and a cap insulating film. The unit includes a plurality of electrode films stacked alternately in a first direction with a plurality of inter-electrode insulating films. The pillar pierces the stacked structural unit in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The inner insulating film is provided between the memory layer and the semiconductor pillar. The outer insulating film is provided between the memory layer and the electrode films. The cap insulating film is provided between the outer insulating film and the electrode films, and the cap insulating film has a higher relative dielectric constant than the outer insulating film.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括层叠结构单元，半导体柱，存储层，内绝缘膜，外绝缘膜和帽绝缘膜。 该单元包括在多个电极间绝缘膜上沿第一方向交替堆叠的多个电极膜。 支柱沿第一方向刺穿层叠的结构单元。 存储层设置在电极膜和半导体柱之间。 内部绝缘膜设置在存储层和半导体柱之间。 外绝缘膜设置在存储层和电极膜之间。 帽绝缘膜设置在外绝缘膜和电极膜之间，并且帽绝缘膜具有比外绝缘膜更高的相对介电常数。