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    Memory cells, integrated devices, and methods of forming memory cells
    32.
    发明授权
    Memory cells, integrated devices, and methods of forming memory cells 有权
    存储单元，集成器件和形成存储单元的方法

    公开(公告)号：US09299930B2

    公开(公告)日：2016-03-29

    申请号：US14225111

    申请日：2014-03-25

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Ugo Russo ,  Agostino Pirovano ,  Simone Lavizzari

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/128 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1675

    Abstract: Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. Some embodiments include a method of forming a memory cell. Chalcogenide material may be formed over heater material. Electrically conductive material may be formed over the chalcogenide material. A thermal sink may be formed between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material.

    Abstract translation: 一些实施例包括集成设备，诸如存储器单元。 这些装置可以包括硫族化物材料，在硫族化物材料上的导电材料，以及在导电材料和硫族化物材料之间的散热器。 散热器可以是包括与导电材料相同的元件的组合物，并且包括与硫族化物材料相同的元件。 一些实施例包括形成存储器单元的方法。 可以在加热器材料上形成硫族化物材料。 可以在硫族化物材料上形成导电材料。 可以在导电材料和硫族化物材料之间形成散热器。 散热器可以是包括与导电材料相同的元件的组合物，并且包括与硫族化物材料相同的元件。

    Memory Cells, Memory Arrays, and Methods of Forming Memory Cells and Arrays
    34.
    发明申请
    Memory Cells, Memory Arrays, and Methods of Forming Memory Cells and Arrays 有权
    内存单元，内存阵列和形成内存单元和阵列的方法

    公开(公告)号：US20150325627A1

    公开(公告)日：2015-11-12

    申请号：US14799467

    申请日：2015-07-14

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Giorgio Servalli ,  Carmela Cupeta ,  Fabio Pellizzer

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L45/1293 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675

    Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

    Abstract translation: 一些实施例包括形成存储器单元的方法。 加热器结构形成在电节点阵列上，相变材料跨过加热器结构形成。 相变材料被图案化成多个限制结构，其中限制结构与加热器结构一一对应，并且通过一个或多个完全横向围绕每个限制结构的绝缘材料彼此间隔开 。 一些实施例包括在电节点阵列上具有加热器结构的存储器阵列。 密闭相变材料结构在加热器结构之上，并且与加热器结构一一对应。 受限制的相变材料结构通过一个或多个完全横向围绕每个限定相变材料结构的绝缘材料彼此间隔开。

    Memory Arrays and Methods of Forming Memory Arrays
    36.
    发明申请
    Memory Arrays and Methods of Forming Memory Arrays 有权
    内存数组和形成内存数组的方法

    公开(公告)号：US20150280117A1

    公开(公告)日：2015-10-01

    申请号：US14226643

    申请日：2014-03-26

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Andrea Redaelli

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1293 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/128 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1675

    Abstract: Some embodiments include memory arrays having a plurality of memory cells vertically between bitlines and wordlines. The memory cells contain phase change material. Heat shields are laterally between immediately adjacent memory cells along a bitline direction. The heat shields contain electrically conductive material and are electrically connected with the bitlines. Some embodiments include memory arrays having a plurality of memory cells arranged in a first grid. The first grid has columns along a first direction and has rows along a second direction substantially orthogonal to the first direction. First heat shields are between adjacent memory cells along the first direction and are arranged in a second grid offset from the first grid along the first direction. Second heat shields are between adjacent memory cells along the second direction, and are arranged lines in lines extending along the first direction. Some embodiments include methods for forming memory arrays.

    Abstract translation: 一些实施例包括在位线和字线之间垂直地具有多个存储单元的存储器阵列。 存储单元包含相变材料。 热屏蔽沿着位线方向横向位于紧邻的存储单元之间。 隔热罩包含导电材料并与位线电连接。 一些实施例包括具有布置在第一网格中的多个存储单元的存储器阵列。 第一格栅具有沿着第一方向的列，并且沿着与第一方向大致正交的第二方向具有列。 第一热屏蔽沿着第一方向位于相邻存储单元之间，并且沿着第一方向布置成与第一格栅偏移的第二格栅。 第二隔热板沿着第二方向位于相邻存储单元之间，并沿着第一方向延伸的线排列。 一些实施例包括用于形成存储器阵列的方法。

    Memory constructions
    37.
    发明授权
    Memory constructions 有权

    公开(公告)号：US08872150B2

    公开(公告)日：2014-10-28

    申请号：US14242706

    申请日：2014-04-01

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Agostino Pirovano

    IPC: H01L29/02 ,  H01L45/00

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/00 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144

    Abstract: Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors.

    Three-dimensional memory array
    39.
    发明授权
    Three-dimensional memory array 有权

    公开(公告)号：US11574957B2

    公开(公告)日：2023-02-07

    申请号：US17320785

    申请日：2021-05-14

    Applicant: Micron Technology, Inc.

    Inventor： Anna Maria Conti ,  Andrea Redaelli ,  Agostino Pirovano

    IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.

    Self-aligned memory decks in cross-point memory arrays
    40.
    发明授权
    Self-aligned memory decks in cross-point memory arrays 有权

    公开(公告)号：US11489117B2

    公开(公告)日：2022-11-01

    申请号：US17308444

    申请日：2021-05-05

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Andrea Redaelli ,  Innocenzo Tortorelli

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.

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