公开(公告)号：US10395697B1

公开(公告)日：2019-08-27

申请号：US15892118

申请日：2018-02-08

Applicant: Micron Technology, Inc.

Inventor： Mahdi Jamali ,  William A. Melton ,  Daniele Vimercati ,  Xinwei Guo ,  Yasuko Hattori

IPC: G11C7/06

Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.

公开(公告)号：US20190122718A1

公开(公告)日：2019-04-25

申请号：US16184300

申请日：2018-11-08

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

Abstract: Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate in a non-volatile mode and then operate in a volatile mode following a command initiated by a controller while the cell is operating in the non-volatile mode. The memory cell may operate in the volatile mode and then operate in the non-volatile mode following a subsequent command. In some examples, one memory cell of the memory array may operate in the non-volatile mode while another memory cell of the memory array operates in the volatile mode.

公开(公告)号：US20190067206A1

公开(公告)日：2019-02-28

申请号：US15691055

申请日：2017-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Daniele Vimercati

IPC: H01L23/552 ,  H01L23/528 ,  H01L27/108 ,  H01L27/11507 ,  G11C11/22 ,  G11C11/4091 ,  G11C11/409

CPC classification number: H01L23/552 ,  G11C7/08 ,  G11C7/1051 ,  G11C7/1096 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/408 ,  G11C11/4085 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/82 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/10885 ,  H01L27/11507 ,  H01L27/11514

Abstract: Apparatuses and methods for memory that includes a first memory cell including a storage component having a first end coupled to a plate line and a second end coupled to a digit line, and a second memory cell including a storage component having a first end coupled to a digit line and a second end coupled to a plate line, wherein the digit line of the second memory cell is adjacent to the plate line of the first memory cell.

公开(公告)号：US10192606B2

公开(公告)日：2019-01-29

申请号：US15090789

申请日：2016-04-05

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

Abstract: A ferroelectric capacitor of a memory cell may be in electronic communication with a sense capacitor through a digit line. The digit line may be virtually grounded during memory cell sensing, limiting or avoiding voltage drop across the digit line, and allowing all or substantially all of the stored charge of the ferroelectric capacitor to be extracted and transferred to the sense capacitor. Virtually grounding the digit line may be achieved by activating a switching component (e.g., a p-type field-effect transistor) that is electronic communication with the digit line. The charge of the ferroelectric capacitor may be transferred through the switching component. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.

公开(公告)号：US10170173B2

公开(公告)日：2019-01-01

申请号：US15847583

申请日：2017-12-19

Applicant: Micron Technology, Inc.

Inventor： Xinwei Guo ,  Daniele Vimercati

IPC: G11C11/22

Abstract: Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell.

公开(公告)号：US20180358072A1

公开(公告)日：2018-12-13

申请号：US15618393

申请日：2017-06-09

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/2275 ,  G11C11/2293

Abstract: Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate in a non-volatile mode and then operate in a volatile mode following a command initiated by a controller while the cell is operating in the non-volatile mode. The memory cell may operate in the volatile mode and then operate in the non-volatile mode following a subsequent command. In some examples, one memory cell of the memory array may operate in the non-volatile mode while another memory cell of the memory array operates in the volatile mode.

公开(公告)号：US20180114559A1

公开(公告)日：2018-04-26

申请号：US15847583

申请日：2017-12-19

Applicant: Micron Technology, Inc.

Inventor： Xinwei Guo ,  Daniele Vimercati

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2275

Abstract: Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a ferroelectric memory cell or cells is described. The scheme employs a charge mirror to extract the full charge difference between the two states of a selected memory cell. The charge mirror may transfer the memory cell polarization charge to an amplification capacitor. The signal on the amplification capacitor may then be compared with a reference voltage to detect the logic state of the memory cell.

公开(公告)号：US20170287541A1

公开(公告)日：2017-10-05

申请号：US15090789

申请日：2016-04-05

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221

Abstract: A ferroelectric capacitor of a memory cell may be in electronic communication with a sense capacitor through a digit line. The digit line may be virtually grounded during memory cell sensing, limiting or avoiding voltage drop across the digit line, and allowing all or substantially all of the stored charge of the ferroelectric capacitor to be extracted and transferred to the sense capacitor. Virtually grounding the digit line may be achieved by activating a switching component (e.g., a p-type field-effect transistor) that is electronic communication with the digit line. The charge of the ferroelectric capacitor may be transferred through the switching component. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.

公开(公告)号：US09406363B2

公开(公告)日：2016-08-02

申请号：US14261674

申请日：2014-04-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gerald Barkley ,  Efrem Bolandrina ,  Daniele Vimercati

IPC: G11C8/00 ,  G11C8/10 ,  G11C5/02 ,  G11C8/14

CPC classification number: G11C8/10 ,  G11C5/025 ,  G11C8/14

Abstract: A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory blocks have every other wordline coupled to one adjacent decoder circuit, and the remaining wordlines coupled to another adjacent decoder circuit.

Abstract translation: 存储器件包括在相邻存储器块之间共享组件的字线解码器电路。 字线解码器电路包括多个电平，其中至少一个电平被分离，驱动一个相邻存储器块中的一半字线并驱动另一相邻存储器块中的一半字线。 存储器块具有耦合到一个相邻解码器电路的每隔一个字线，并且剩余字线耦合到另一相邻解码器电路。

公开(公告)号：US12237020B2

公开(公告)日：2025-02-25

申请号：US17888298

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22 ,  G11C13/00 ,  G11C16/12 ,  G11C16/26

Abstract: Methods, systems, and devices for storing bits, such as N−1 bits, with cells, such as N cells, in a memory device are described. A memory device may generate a first sensing voltage that is based on a first voltage of a first digit line and a second voltage of a second digit line. The memory device may also generate a second sensing voltage that is based on a third voltage of a third digit line and a fourth voltage of a fourth digit line. The memory device may then determine a bit value based at least in part on a difference between the first sensing voltage and the second sensing voltage.