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公开(公告)号：US20240274183A1
公开(公告)日：2024-08-15
申请号：US18582185
申请日：2024-02-20
Applicant: Micron Technology, Inc.
Inventor： Efrem Bolandrina , Andrea Martinelli , Christophe Vincent Antoine Laurent , Ferdinando Bedeschi
IPC: G11C11/408 , G11C11/4074 , G11C11/4091 , G11C11/4093
CPC classification number: G11C11/4082 , G11C11/4074 , G11C11/4085 , G11C11/4091 , G11C11/4093
Abstract: Methods, systems, and devices for parallel access in a memory array are described. A set of memory cells of a memory device may be associated with an array of conductive structures, where such structures may be coupled using a set of transistors or other switching components that are activated by a first driver. The set of memory cells may be divided into two or more subsets of memory cells, where each subset may be associated with a respective second driver for driving access currents through memory cells of the subset. Two or more of such second drivers may operate concurrently, which may support distributing current or distributing associated circuit structures across a different footprint of the memory device than other different implementations with a single such second driver.
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公开(公告)号：US20220199140A1
公开(公告)日：2022-06-23
申请号：US17563395
申请日：2021-12-28
Applicant: Micron Technology, Inc.
Inventor： Efrem Bolandrina , Ferdinando Bedeschi
IPC: G11C11/22
Abstract: Techniques are described for maintaining a stable voltage difference in a memory device, for example, during a critical operation (e.g., a sense operation). The voltage difference to be maintained may be a read voltage across a memory cell or a difference associated with a reference voltage, among other examples. A component (e.g., a local capacitor) may be coupled, before the operation, with a node biased to a first voltage (e.g., a global reference voltage) to sample a voltage difference between the first voltage and a second voltage while the circuitry is relatively quiet (e.g., not noisy). The component may be decoupled from the node before the operation such that a node of the component (e.g., a capacitor) may be allowed to float during the operation. The voltage difference across the component may remain stable during variations in the second voltage and may provide a stable voltage difference during the operation.
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公开(公告)号：US09406363B2
公开(公告)日：2016-08-02
申请号：US14261674
申请日：2014-04-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Gerald Barkley , Efrem Bolandrina , Daniele Vimercati
Abstract: A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory blocks have every other wordline coupled to one adjacent decoder circuit, and the remaining wordlines coupled to another adjacent decoder circuit.
Abstract translation: 存储器件包括在相邻存储器块之间共享组件的字线解码器电路。 字线解码器电路包括多个电平，其中至少一个电平被分离，驱动一个相邻存储器块中的一半字线并驱动另一相邻存储器块中的一半字线。 存储器块具有耦合到一个相邻解码器电路的每隔一个字线，并且剩余字线耦合到另一相邻解码器电路。
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公开(公告)号：US12249362B2
公开(公告)日：2025-03-11
申请号：US18120133
申请日：2023-03-10
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Efrem Bolandrina
Abstract: Methods, systems, and devices for a single plate configuration and memory array operation are described. A non-volatile memory array may utilize a single plate to cover a subset of the array. One or more memory cells of the subset may be selected by operating the plate and an access line of an unselected memory cell at a fixed voltage. A second voltage may be applied to an access line of the selected cell, and subsequently reduced to perform an access operation. Removing the applied voltage may allow for the memory cell to undergo a recovery period prior to a subsequent access operation.
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公开(公告)号：US20240237358A1
公开(公告)日：2024-07-11
申请号：US18407074
申请日：2024-01-08
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Corrado Villa , Stefan Frederik Schippers , Efrem Bolandrina
CPC classification number: H10B63/34 , G11C13/0004 , G11C13/003 , H10B63/845 , G11C2213/71 , G11C2213/79
Abstract: The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.
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Patent Agency Ranking
公开(公告)号：US20240221798A1
公开(公告)日：2024-07-04
申请号：US18408228
申请日：2024-01-09
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Efrem Bolandrina
CPC classification number: G11C7/1063 , G11C7/1048 , G11C7/109 , G11C8/18
Abstract: Methods, systems, and devices for techniques for indicating row activation are described. A memory device may receive an indication associated with an activation command, which may enable the memory device to begin some aspects of an activation operation before receiving the associated activation command. The indication may include a location of a next row to access as part of the activation command. The indication may be included in a previous activation command or in a precharge command. The memory device may begin activation operations for the next row before the precharge operation of the current row is complete. The memory device may receive the activation command for the next row after receiving the indication, and may complete the activation operations upon receiving the activation command.
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公开(公告)号：US20240071483A1
公开(公告)日：2024-02-29
申请号：US17898392
申请日：2022-08-29
Applicant: Micron Technology, Inc.
Inventor： Christophe Vincent Antoine Laurent , Francesco Mastroianni , Andrea Martinelli , Efrem Bolandrina , Lucia Di Martino , Riccardo Muzzetto , Zhongyuan Lu , Karthik Sarpatwari , Nevil N. Gajera
CPC classification number: G11C11/5628 , G06F3/0679 , G06F12/0246
Abstract: Disclosed are techniques for correcting drift accumulation in memory cells. In some aspects, the techniques described herein relate to a memory device including: a memory array, the memory array including a set of memory cells; and a memory controller configured to read data from the memory array, the memory controller configured to: sense a first distribution of the set of memory cells, detect a missing cell in the first distribution, increase a voltage on the missing cell causing the missing cell to be read as part of the first distribution, detect that a second memory cell in a second distribution was read while sensing the first distribution, and mask the second memory cell and mark the second memory cell as belonging to the second distribution.
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公开(公告)号：US11877457B2
公开(公告)日：2024-01-16
申请号：US16976411
申请日：2020-05-25
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Corrado Villa , Stefan Frederik Schippers , Efrem Bolandrina
CPC classification number: H10B63/34 , G11C13/003 , G11C13/0004 , H10B63/845 , G11C2213/71 , G11C2213/79
Abstract: The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.
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公开(公告)号：US20230395136A1
公开(公告)日：2023-12-07
申请号：US18196268
申请日：2023-05-11
Applicant: Micron Technology, Inc.
Inventor： Andrea Martinelli , Claudia Palattella , Christophe Vincent Antoine Laurent , Ferdinando Bedeschi , Efrem Bolandrina
IPC: G11C11/4096 , G11C11/4078 , G11C11/4099
CPC classification number: G11C11/4096 , G11C11/4078 , G11C11/4099
Abstract: Methods, systems, and devices for memory array seasoning are described. Some memory cells may have an undesirably high threshold voltage and thus a seasoning operation may be performed on a target memory cell. To season the target memory cell, a bit line and a word line associated with the cell may be activated. Additionally or alternatively, a word line coupled with a second memory cell (e.g., a helper memory cell) that shares the activated bit line may be activated. Accordingly, current flowing across the target memory cell may be increased, which may reduce its threshold voltage.
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公开(公告)号：US20230395135A1
公开(公告)日：2023-12-07
申请号：US17864046
申请日：2022-07-13
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Efrem Bolandrina , Innocenzo Tortorelli
IPC: G11C11/4096 , G11C11/4091 , G11C11/4093 , G11C11/4076
CPC classification number: G11C11/4096 , G11C11/4091 , G11C11/4093 , G11C11/4076
Abstract: Systems, methods, and apparatus related to memory devices (e.g., storage class memory). In one approach, a memory device has a memory array including memory cells arranged as differential memory cell pairs, with each pair storing a single logical bit. The memory device has a controller that receives a command from a host to initiate a read operation. The memory cell pair is selected using bitlines and a common wordline. A partition of the memory array is accessed to read the data stored by the memory cell pair, and then store the read data in a latch for sending to the host. In response to accessing the partition, a counter is incremented. The controller statistically determines whether to perform a refresh operation for the partition based on comparing the current value of the counter to a value previously generated by a random number generator.
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