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公开(公告)号：US20210034486A1
公开(公告)日：2021-02-04
申请号：US17073166
申请日：2020-10-16
Applicant: Micron Technology, Inc.
Inventor： Samuel E. Bradshaw , Justin Eno
Abstract: A technique of receiving a write transaction directed to a group of memory parcels of a memory device from a client source. The technique determines a state of a first indicator used to indicate which one of two data structures contains a newer mapping of the group of memory parcels, while the other data structure contains an older mapping of the group of memory parcels. The technique determines a state of a second indicator used to indicate which one of the two data structures is in current use for the group of memory parcels and compares the states of the two indicators. When a data structure in current use does not contain the newer mapping, the technique changes the state of the second indicator to the state of the first indicator. The technique writes content of the write transaction to storage locations based on the newer mapping.
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公开(公告)号：US10658067B2
公开(公告)日：2020-05-19
申请号：US15979285
申请日：2018-05-14
Applicant: Micron Technology, Inc.
Inventor： Samuel E. Bradshaw , Justin Eno
Abstract: Exemplary methods, apparatuses, and systems include a controller that determines that a group of memory cells of a first memory device has an elevated error rate. In response to determining the elevated error rate, the controller identifies a spare group of memory cells. The group of memory cells and the spare group of memory cells span a first dimension and a second dimension that is orthogonal to the first dimension. The controller reads a portion of a logical unit from the group of memory cells along the first dimension of the group. The controller further determines that the group of memory cells and the spare group of memory cells have strong disturb effects in different dimensions and, in response to that determination, writes the portion of the logical unit to the spare group of memory cells along the second dimension of the spare group.
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公开(公告)号：US20190354429A1
公开(公告)日：2019-11-21
申请号：US15983647
申请日：2018-05-18
Applicant: Micron Technology, Inc.
Inventor： Samuel E. Bradshaw , Justin Eno , Sean Stephen Eilert , Sai Krishna Mylavarapu
Abstract: Exemplary methods, apparatuses, and systems include a memory controller receiving a user payload to be written to a memory. The memory controller determines a plurality of locations within the memory within which the user payload will be written. After detecting the destination of the user payload, the memory controller detects, within a data structure, the presence of an identifier of a first location within a user data portion of the plurality of locations. The memory controller writes the user payload to the user data portion of the plurality of locations and, in response to detecting the presence of the identifier in the data structure, writes a copy of one or more bits in the user payload written to the first location to a spare data portion of the plurality of locations.
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公开(公告)号：US20250165160A1
公开(公告)日：2025-05-22
申请号：US19033755
申请日：2025-01-22
Applicant: Micron Technology, Inc.
Inventor： Sean S. Eilert , Justin Eno , Ameen D. Akel
Abstract: Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.
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公开(公告)号：US12299291B2
公开(公告)日：2025-05-13
申请号：US17369869
申请日：2021-07-07
Applicant: Micron Technology, Inc.
Inventor： Sean S. Eilert , Justin Eno , Ameen D. Akel
Abstract: Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.
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Patent Agency Ranking
公开(公告)号：US20240086100A1
公开(公告)日：2024-03-14
申请号：US17931262
申请日：2022-09-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Justin Eno , Sean S. Eilert , Ameen D. Akel , Kenneth M. Curewitz
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0673
Abstract: A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.
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公开(公告)号：US11740899B2
公开(公告)日：2023-08-29
申请号：US17577977
申请日：2022-01-18
Applicant: Micron Technology, Inc.
Inventor： Sean S. Eilert , Ameen D. Akel , Justin Eno , Brian Hirano
IPC: G06F1/3225 , G06F16/27 , G06F9/30 , G06F13/16
CPC classification number: G06F9/30036 , G06F9/3004 , G06F13/1668
Abstract: Methods, systems, and devices for in-memory associative processing are described. An apparatus may receive a set of instructions that indicate a first vector and a second vector as operands for a computational operation. The apparatus may select, from a set of vector mapping schemes, a vector mapping scheme for performing the computational operation using associative processing. The apparatus may write the first vector and the second vector to a set of planes each comprising an array of content-addressable memory cells based on the selected vector mapping scheme.
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公开(公告)号：US20230071764A1
公开(公告)日：2023-03-09
申请号：US17943581
申请日：2022-09-13
Applicant: Micron Technology, Inc.
Inventor： Sean S. Eilert , William A. Melton , Justin Eno
IPC: G06F11/10 , G06F12/0875
Abstract: Methods, systems, and devices for error caching techniques for improved error correction in a memory device are described. An apparatus, such as a memory device, may use an error cache to store indications of memory cells identified as defective and may augment an error correction procedure using the stored indications. If one or more errors are detected in data read from the memory array, the apparatus may check the error cache, and if a bit of the data is indicated as being associated with a defective cell, the bit may be inverted. After such inversion, the data may be checked for errors again. If the inversion corrects an error, the resulting data may be error-free or may include a reduced quantity of errors that may be correctable using an error correction scheme.
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公开(公告)号：US20230069790A1
公开(公告)日：2023-03-02
申请号：US17577977
申请日：2022-01-18
Applicant: Micron Technology, Inc.
Inventor： Sean S. Eilert , Ameen D. Akel , Justin Eno , Brian Hirano
Abstract: Methods, systems, and devices for in-memory associative processing are described. An apparatus may receive a set of instructions that indicate a first vector and a second vector as operands for a computational operation. The apparatus may select, from a set of vector mapping schemes, a vector mapping scheme for performing the computational operation using associative processing. The apparatus may write the first vector and the second vector to a set of planes each comprising an array of content-addressable memory cells based on the selected vector mapping scheme.
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公开(公告)号：US20220405169A1
公开(公告)日：2022-12-22
申请号：US17861013
申请日：2022-07-08
Applicant: Micron Technology, Inc.
Inventor： Justin Eno , William A. Melton , Sean S. Eilert
Abstract: Methods, systems, and devices for adaptive parity techniques for a memory device are described. An apparatus, such as a memory device, may use one or more error correction code (ECC) schemes, an error cache, or both to support access operations. The memory device may receive a command from a host device to read or write data. If the error cache includes an entry for the data, the memory device may read or write the data using a first ECC scheme. If the error cache does not include an entry for the data, the memory device may read or write the data without using an ECC scheme or using a second ECC scheme different than the first ECC scheme.
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