公开(公告)号：US20240168536A1

公开(公告)日：2024-05-23

申请号：US18503319

申请日：2023-11-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Liang Yu ,  Jonathan S. Parry ,  Chulbum Kim ,  Tal Sharifie ,  Stephen Hanna

IPC: G06F1/3225

CPC classification number: G06F1/3225

Abstract: A memory device includes a set of memory dies, each memory die of the set of memory dies including a memory array and first control logic operatively coupled to the memory array, and an application-specific integrated circuit (ASIC) including a general-purpose input/output component (GPIO) including at least one digital pad communicably coupled to each memory die of the set of memory dies, and second control logic, operatively coupled to memory, to perform operations related to peak power management (PPM).

公开(公告)号：US20240152295A1

公开(公告)日：2024-05-09

申请号：US18503246

申请日：2023-11-07

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0679

Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies including a memory array and control logic, operatively coupled with the memory array, to perform operations including identifying a data path operation with respect to the memory die. The memory die is associated with a channel. The operations further include determining, based on at least one value derived from a current budget ready status and a cache ready status, whether the channel is ready for the memory die to handle the data path operation, and in response to determining that the channel is ready for the memory die to handle the data path operation, causing the data path operation to be handled by the memory die.

公开(公告)号：US20240061592A1

公开(公告)日：2024-02-22

申请号：US18231338

申请日：2023-08-08

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Jonathan S. Parry ,  Luca Nubile ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Liang Yu ,  Jeremy Binfet ,  Walter Di Francesco ,  Daniel J. Hubbard ,  Luigi Pilolli

IPC: G06F3/06 ,  G06F1/3234

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  G06F1/3275

Abstract: A method includes receiving a request to perform a memory access operation, wherein the memory access operation includes a set of sub-operations, selecting a current quantization data structure from a plurality of current quantization data structures, wherein each current quantization data structure of the plurality of current quantization data structures maintains, for each sub-operation of the set of sub-operations, a respective current quantization value reflecting an amount of current that is consumed by the respective sub-operation based on a set of peak power management (PPM) operation parameters, and causing the memory access operation to be performed using PPM based on the current quantization data structure.

公开(公告)号：US20230195312A1

公开(公告)日：2023-06-22

申请号：US17990126

申请日：2022-11-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Liang Yu ,  Jonathan S. Parry ,  Fumin Gu ,  John Paul Aglubat

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0634 ,  G06F3/0679

Abstract: A memory device includes memory dies, each memory die including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations. The PPM operations include causing a memory die to be placed in a suspended state to suspend execution of a first media access operation with a reserved current budget, receiving a set of requests to execute at least a second media access operation during the suspended state, and in response receiving the set of requests, handling the set of requests by implementing current budget arbitration logic with respect to the reserved current budget.

公开(公告)号：US20230067294A1

公开(公告)日：2023-03-02

申请号：US17983177

申请日：2022-11-08

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  Jonathan Scott Parry ,  Luigi Pilolli

IPC: G06F3/06 ,  G06F12/0802

Abstract: A variety of applications can include a memory device having a memory die designed to control a power budget for a cache and a memory array of the memory die. A first flag received from a data path identifies a start of a cache operation on the data and a second flag from the data path identifies an end of the cache operation. A controller for peak power management can be implemented to control the power budget based on determination of usage of current associated with the cache from the first and second flags. In various embodiments, the controller can be operable to feedback a signal to a memory controller external to the memory die to adjust an operating speed of an interface from the memory controller to the memory die. Additional devices, systems, and methods are discussed.

公开(公告)号：US20220392546A1

公开(公告)日：2022-12-08

申请号：US17738126

申请日：2022-05-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Liang Yu ,  Jeremy Binfet

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08

Abstract: A memory device might include a controller configured to cause the memory device to generate a first sum of expected peak current magnitudes for a plurality of memory devices, and generate a second sum of expected peak current magnitudes for a subset of the plurality of memory devices, if the memory device were to initiate a next phase of an access operation in a selected operating mode; to compare the first sum to a first current demand budget for the plurality of the memory devices; to compare the second sum to a second current demand budget for the subset of memory devices; and to initiate the next phase of the access operation in the selected operating mode in response to the first sum being less than or equal to the first current demand budget and the second sum being less than or equal to the second current demand budget.

公开(公告)号：US20220199192A1

公开(公告)日：2022-06-23

申请号：US17249400

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Liang Yu

IPC: G11C29/50 ,  G06F1/3225

Abstract: A memory device includes a first memory die of a plurality of memory dies, the first memory die comprising a first memory array and a first power management component, wherein the first power management component is configured to send a first test value to one or more other power management components on one or more other memory dies of the plurality of memory dies during a first power management cycle of a first power management token loop. The memory device further includes a second memory die of the plurality of memory dies, the second memory die comprising a second memory array and a second power management component, wherein the second power management component is configured to receive the first test value from the first power management component during the first power management cycle of the first power management token loop and send a second test value to the one or more other power management components on the one or more other memory dies of the plurality of memory dies during a second power management cycle of a second power management token loop. At least one of the first power management component or the second power management component is configured to compare the first test value and the second test value to a set of expected values to determine whether signal connections between the first power management component and the second power management component are functional.

公开(公告)号：US20220171546A1

公开(公告)日：2022-06-02

申请号：US17110103

申请日：2020-12-02

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  Jonathan Scott Parry ,  Luigi Pilolli

IPC: G06F3/06 ,  G06F12/0802

Abstract: A variety of applications can include a memory device having a memory die designed to control a power budget for a cache and a memory array of the memory die. A first flag received from a data path identifies a start of a cache operation on the data and a second flag from the data path identifies an end of the cache operation. A controller for peak power management can be implemented to control the power budget based on determination of usage of current associated with the cache from the first and second flags. In various embodiments, the controller can be operable to feedback a signal to a memory controller external to the memory die to adjust an operating speed of an interface from the memory controller to the memory die. Additional devices, systems, and methods are discussed.

公开(公告)号：US20220100431A1

公开(公告)日：2022-03-31

申请号：US17549181

申请日：2021-12-13

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  Jonathan Parry

IPC: G06F3/06 ,  G11C16/26

Abstract: A system to send a first command to execute an initialization process on a first memory die of a plurality of memory dies of a memory sub-system. The system reads a bit value indicating that the first memory die is executing a low peak current draw phase of the initialization process. In response to reading the bit value, sending a second command to a second memory die of the plurality of memory dies of the memory sub-system, the second command to execute the initialization process on the second memory die.

公开(公告)号：US20210357149A1

公开(公告)日：2021-11-18

申请号：US16875464

申请日：2020-05-15

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  Jonathan Parry

IPC: G06F3/06 ,  G11C16/26

Abstract: A system to send a first command to a first memory die of a plurality of memory dies of a memory sub-system the first command to execute an initialization process. The system reads a first bit value from the first memory die, the first bit value indicating the first memory die is executing a peak current phase of the initialization process. The system reads a second bit value from the first memory die, the second bit value indicating the first memory die is executing a safe phase of the initialization process. In response to reading the second bit value, a second command is sent to a second memory die to execute the initialization process.