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    HOST ASSISTED OPERATIONS IN MANAGED MEMORY DEVICES
    34.
    发明申请
    HOST ASSISTED OPERATIONS IN MANAGED MEMORY DEVICES 有权

    公开(公告)号：US20230042487A1

    公开(公告)日：2023-02-09

    申请号：US17971298

    申请日：2022-10-21

    Applicant: Micron Technology, Inc.

    Inventor： Nadav Grosz ,  Jonathan Scott Parry

    IPC: G06F12/14 ,  G06F21/78 ,  G06F12/02

    Abstract: Devices and techniques for efficient host assisted logical-to-physical (L2P) mapping are described herein. For example, a command can be executed that results in a change as to which physical address of a memory device corresponds to a logical address. The change can be obfuscated as part of an obfuscated L2P map for the memory device and written to storage on the memory device. The change can then be provided a host from the storage.

    MULTI-TIER CACHE FOR A MEMORY SYSTEM
    35.
    发明申请
    MULTI-TIER CACHE FOR A MEMORY SYSTEM 有权

    公开(公告)号：US20220188242A1

    公开(公告)日：2022-06-16

    申请号：US17546618

    申请日：2021-12-09

    Applicant: Micron Technology, Inc.

    Inventor： Kulachet Tanpairoj ,  Nadav Grosz ,  James Fitzpatrick ,  Jianmin Huang

    IPC: G06F12/0897 ,  G06F12/0811 ,  G06F12/02

    Abstract: Methods, systems, and devices for a multi-tier cache for a memory system are described. A memory device may include memory cells configured as cache storage and memory cells configured as main storage. The cache storage may be a multi-tier cache and may include sets of different types of memory cells or memory cells operated as different types of memory cells, with different latencies, storage densities, or other performance characteristics. The memory device or a controller or host system for the memory device may determine the set of memory cells within the multi-tier cache to which a set of data is to be written, or may move the set of data within the multi-tier cache or between the multi-tier cache and the main storage, based on one or more of a variety of performance considerations.

    Sequential data optimized sub-regions in storage devices
    36.
    发明授权
    Sequential data optimized sub-regions in storage devices 有权

    公开(公告)号：US11294585B2

    公开(公告)日：2022-04-05

    申请号：US17129087

    申请日：2020-12-21

    Applicant: Micron Technology, Inc.

    Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Scott Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Christian M. Gyllenskog ,  Kulachet Tanpairoj

    IPC: G06F3/06 ,  G06F12/02

    Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

    HOST INQUIRY RESPONSE GENERATION IN A MEMORY DEVICE
    37.
    发明申请
    HOST INQUIRY RESPONSE GENERATION IN A MEMORY DEVICE 有权

    公开(公告)号：US20220083263A1

    公开(公告)日：2022-03-17

    申请号：US17532020

    申请日：2021-11-22

    Applicant: Micron Technology, Inc.

    Inventor： Nadav Grosz ,  David Aaron Palmer

    IPC: G06F3/06

    Abstract: Devices and techniques for generating a response to a host with a memory device are provided. A first command from a host can be executed. A status for the first command can he determined. An inquiry from the host about a second command can be received after execution of the first command has begun. A response can be made to the inquiry that includes information about the second command and the status for the first command.

    DATA TECHNIQUES FOR SYSTEM BOOT PROCEDURES
    38.
    发明申请
    DATA TECHNIQUES FOR SYSTEM BOOT PROCEDURES 有权

    公开(公告)号：US20210373908A1

    公开(公告)日：2021-12-02

    申请号：US16888212

    申请日：2020-05-29

    Applicant: Micron Technology, Inc.

    Inventor： Qing Liang ,  Jonathan S. Parry ,  Nadav Grosz

    IPC: G06F9/4401 ,  G06F12/10

    Abstract: Methods, systems, and devices for data techniques for system boot procedures are described. A memory system may receive, from a host system, a set of commands as part of a boot procedure of the host system. The set of commands may request data stored in a first set of locations of a memory array of the memory system. The memory system may retrieve, as part of the boot procedure, the data from the first set of locations based on receiving the commands. The memory system may determine an order that the data is retrieved from each location of the first set of locations. The memory system may transfer the data from the first set of locations to a second set of locations based on the order that the data is retrieved from each location of the first set of locations.

    READ PREDICTION DURING A SYSTEM BOOT PROCEDURE
    39.
    发明申请
    READ PREDICTION DURING A SYSTEM BOOT PROCEDURE 有权

    公开(公告)号：US20210373907A1

    公开(公告)日：2021-12-02

    申请号：US16888198

    申请日：2020-05-29

    Applicant: Micron Technology, Inc.

    Inventor： Qing Liang ,  Nadav Grosz ,  Jonathan S. Parry

    IPC: G06F9/4401 ,  G06F12/0877

    Abstract: Methods, systems, and devices for read prediction during a system boot procedure are described. A memory device may identify a command for a boot procedure and transfer data stored in a memory array to a cache of the memory device. In some cases, the memory device may prefetch data used during the boot procedure and thereby improve the latency of the boot procedure. When the memory device receives a command that requests data stored in the memory array as part of the boot procedure, the memory device may identify a cache hit based on prefetching the requested data before the command is received. In such cases, the memory device may retrieve the prefetched data from the cache.

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