公开(公告)号：US11087829B2

公开(公告)日：2021-08-10

申请号：US16926476

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  George B. Raad ,  Debra M. Bell ,  Markus H. Geiger ,  Anthony D. Veches

IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/406

Abstract: Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.

公开(公告)号：US20210201981A1

公开(公告)日：2021-07-01

申请号：US17022030

申请日：2020-09-15

Applicant: Micron Technology, Inc.

Inventor： Gitanjali T. Ghosh ,  Debra M. Bell ,  Arunmozhi R. Subramaniam ,  Roya Baghi ,  Deepika Thumsi Umesh ,  Sue-Fern Ng

IPC: G11C11/408 ,  G11C11/4099 ,  G11C11/4074 ,  G11C11/4076

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor degradations in word line characteristics. The memory device may generate a reference signal in response to an access command directed to a memory array including a plurality of word lines, in some embodiments. The memory array may include a victim word line configured to accumulate adverse effects of executing multiple access commands at the word lines of the memory array. When the degradation in the word line characteristics causes reliability issues (e.g., corrupted data), the memory array is deemed unreliable, and may be blocked from memory operations. The memory device may compare the reference signal and a signal from the victim word line to determine whether preventive measures may be appropriate to avoid (or mitigate) such reliability issues.

公开(公告)号：US11024367B2

公开(公告)日：2021-06-01

申请号：US17017545

申请日：2020-09-10

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C5/02 ,  G11C11/4093 ,  G11C11/406 ,  G11C7/18 ,  H01L25/10 ,  G11C11/4096

Abstract: Memory devices and systems with on-die data transfer capability, and associated methods, are disclosed herein. In one embodiment, a memory device includes an array of memory cells and a plurality of input/output lines operably connecting the array to data pads of the device. In some embodiments, the memory device can further include a global cache and/or a local cache. The memory device can be configured to internally transfer data stored at a first location in the array to a second location in the array without outputting the data from the memory device. To transfer the data, the memory device can copy data on one row of memory cells to another row of memory cells, directly write data to the second location from the first location using data read/write lines of the input/output lines, and/or read the data into and out of the global cache and/or the local cache.

公开(公告)号：US20210064467A1

公开(公告)日：2021-03-04

申请号：US16554931

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Todd M. Buerkle ,  Debra M. Bell ,  Joshua E. Alzheimer

IPC: G06F11/10

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may directly access a portion of memory array that is otherwise reserved for ECC functionality of a memory device. The memory array may correspond to a set of memory addresses, where each memory address of the set corresponds to a first portion of the memory array (e.g., user data plane) and to a second portion of the memory array (e.g., ECC plane). The second portion may be configured to store ECC data or second user data or metadata based on whether the ECC functionality is enabled or disabled. The memory device may determine a command directed to the memory address of the set is configured to access the first portion or the second portion based on a status of a pin associated with the command.

公开(公告)号：US10921996B2

公开(公告)日：2021-02-16

申请号：US16361864

申请日：2019-03-22

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Naveh Malihi

IPC: G06F21/79 ,  G06F3/06 ,  G11C7/06 ,  H03K19/20

Abstract: Apparatuses and methods related to updating data lines for data generation in, for example, a memory device or a computing system that includes a memory device. Updating data lines can include updating a plurality of data lines. The plurality of data lines can provide data form the memory array responsive to a receipt of the access command. The plurality of data lines can also be updated responsive to a determination that an access command received at a memory device is unauthorized.

公开(公告)号：US10910033B2

公开(公告)日：2021-02-02

申请号：US16220742

申请日：2018-12-14

Applicant: Micron Technology, Inc.

Inventor： Stephen Michael Kaminski ,  Anthony D. Veches ,  James S. Rehmeyer ,  Debra M. Bell ,  Dale Herber Hiscock ,  Joshua E. Alzheimer

IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4091

Abstract: Methods, systems, and devices for refresh-related activation in memory are described. A memory device may conduct a refresh operation to preserve the integrity of data. A refresh operation may be associated with a refresh time where the memory device is unable to execute or issue any commands (e.g., access commands). By posting (e.g., saving) one or more commands and/or row addresses during the refresh time, the memory device may be configured to execute the saved commands and/or re-open one or more rows associated with the saved row addresses at a later time (e.g., upon completion of the refresh operation). Accordingly, fewer commands may be issued to activate the memory cells after the refresh time.

公开(公告)号：US20200227113A1

公开(公告)日：2020-07-16

申请号：US16247277

申请日：2019-01-14

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Debra M. Bell ,  George B. Raad ,  Brian P. Callaway ,  Joshua E. Alzheimer

IPC: G11C11/406 ,  G11C11/403 ,  G11C11/408

Abstract: A memory device may include a phase driver circuit that may output a first voltage for refreshing a plurality of memory cells. The memory device may also include a plurality of word line driver circuits that may receive the first voltage via the phase driver circuit, such that each word line driver circuit of the plurality of word line driver circuits may provide the first voltage to a respective word line associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit.

公开(公告)号：US20190272243A1

公开(公告)日：2019-09-05

申请号：US16415841

申请日：2019-05-17

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell

IPC: G06F13/366 ,  G06F13/24 ,  G11C7/00 ,  G06F11/00 ,  G11C7/24 ,  G06F13/16 ,  G06F13/28

Abstract: The present disclosure includes apparatuses and methods related to accessing status information. One example apparatus comprises a host and a memory device coupled to the host. The memory device includes a controller configured to provide, to a status arbiter, a status signal indicating whether a status register of the controller contains generated status information. Responsive to the status signal indicating that the status register contains the generated status information, the controller can also provide the status information from the controller to the status arbiter via a status intermediary.

公开(公告)号：US10303632B2

公开(公告)日：2019-05-28

申请号：US15220177

申请日：2016-07-26

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell

IPC: G06F13/16 ,  G06F13/366 ,  G06F13/24 ,  G06F13/28 ,  G11C7/00 ,  G06F11/00 ,  G11C7/24

Abstract: The present disclosure includes apparatuses and methods related to accessing status information. One example apparatus comprises a host and a memory device coupled to the host. The memory device includes a controller configured to provide, to a status arbiter, a status signal indicating whether a status register of the controller contains generated status information. Responsive to the status signal indicating that the status register contains the generated status information, the controller can also provide the status information from the controller to the status arbiter via a status intermediary.

公开(公告)号：US20180336934A1

公开(公告)日：2018-11-22

申请号：US16048954

申请日：2018-07-30

Applicant: Micron Technology, Inc.

Inventor： Joshua E. Alzheimer ,  Debra M. Bell

IPC: G11C7/06 ,  G11C11/4091 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091

Abstract: The present disclosure includes apparatuses and methods related to scan chain operation in sensing circuitry. A number of embodiments include an apparatus comprising an array of memory cells coupled to sensing circuitry having a sense amplifier and a compute component, the sensing circuitry to receive a scan vector and perform a scan chain operation on the scan vector.