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    Semiconductor device
    31.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07456487B2

    公开(公告)日：2008-11-25

    申请号：US10974810

    申请日：2004-10-28

    申请人： Tsuneo Ogura ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

    发明人： Tsuneo Ogura ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

    IPC分类号： H01L29/739

    CPC分类号： H01L29/1095 ,  H01L29/0834 ,  H01L29/7397

    摘要： This disclosure concerns a semiconductor device that includes a first base layer; second base layers provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers; an emitter layer formed on a surface of the second base layers; a collector layer provided below a second surface of the first base layer, an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being electrically isolated from the emitter layer and the second base layers, wherein the space section includes a semiconductor layer being deeper than the second base layers.

    摘要翻译： 本公开涉及包括第一基底层的半导体器件; 设置在所述第一基底层的第一表面的一部分上的第二基底层; 形成在第二基层的每侧的沟槽; 形成在所述第二基底层的表面上的发射极层; 设置在所述第一基底层的第二表面下方的集电极层，形成在所述沟槽的内壁上的绝缘膜，所述绝缘膜在所述沟槽的底部比在所述沟槽的侧表面上更厚; 形成在沟槽内并由绝缘膜隔离的栅电极; 以及设置在彼此相邻的第二基底层之间的空间部分，所述空间部分与发射极层和第二基底层电隔离，其中所述空间部分包括比所述第二基底层更深的半导体层。

    Method of driving CCD type solid-state imaging device and solid-state imaging apparatus
    32.
    发明申请
    Method of driving CCD type solid-state imaging device and solid-state imaging apparatus 失效
    驱动CCD型固态成像装置和固态成像装置的方法

    公开(公告)号：US20070285546A1

    公开(公告)日：2007-12-13

    申请号：US11806769

    申请日：2007-06-04

    申请人： Tomoki Inoue

    发明人： Tomoki Inoue

    IPC分类号： H04N5/335

    CPC分类号： H04N5/243 ,  H04N5/37213

    摘要： A driving section 4 supplies a reading pulse of ‘H’ to electrodes V1 and V5 simultaneously with completion of exposure to read out electric charges to empty packets below electrodes V1, V2, V5, and V6. Then, the driving section 4 supplies a driving pulse of ‘M’ to electrodes V3 and V7 and a multiplication pulse to the electrodes V2 and V6. At this time, a level of the multiplication pulse supplied to the electrodes V2 and V6 is set so that a potential difference between the electrodes V1 and V3 and the electrode V2 and a potential difference between the electrodes V5 and V7 and the electrode V6 become values required to cause avalanche multiplication. Electric charges accumulated below the electrodes V1 to V3 move into packets formed below the electrodes V2 and V6. The avalanche multiplication occurs at the time of movement. Thus, the electric charges are multiplied.

    摘要翻译： 驱动部分4在完成曝光的同时向电极V 1和V 5提供“H”的读取脉冲，以读出电荷以将电极V 1，V 2，V 5和V 6以下的分组排出。 然后，驱动部分4向电极V 3和V 7提供“M”的驱动脉冲，并向电极V 2和V 6提供乘法脉冲。 此时，提供给电极V 2和V 6的倍增脉冲的电平被设定为使得电极V 1和V 3与电极V 2之间的电位差和电极V 5和V之间的电位差 并且电极V 6成为引起雪崩倍增所需的值。 蓄积在电极V 1至V 3之下的电荷移动到形成在电极V 2和V 6下方的分​​组中。 雪崩乘法发生在运动时。 因此，电荷相乘。

    SEMICONDUCTOR DEVICE
    33.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20070278566A1

    公开(公告)日：2007-12-06

    申请号：US11833401

    申请日：2007-08-03

    申请人： Tsuneo Ogura ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

    发明人： Tsuneo Ogura ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

    IPC分类号： H01L29/78

    CPC分类号： H01L29/1095 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/7394 ,  H01L29/7397

    摘要： A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of a second conductivity type selectively formed in a surface portion of the barrier layer, a source layer of the first conductivity type selectively formed in the surface portion of the barrier layer so as to contact the contact layer and a side wall of the gate insulating film in the trench, and a first main electrode formed so as to contact the contact layer and the source layer.

    摘要翻译： 半导体器件包括第一导电类型的基底层，形成在基底层上的第一导电类型的阻挡层，从阻挡层的表面形成的沟槽到达达到 阻挡层和基底层之间的界面，通过栅极绝缘膜形成在沟槽中的栅极电极，选择性地形成在阻挡层的表面部分中的第二导电类型的接触层，第一导电性的源极层 形成在所述阻挡层的表面部分中以与所述沟槽中的所述接触层和所述栅极绝缘膜的侧壁接触的第一主电极以及与所述接触层和所述源极层接触的第一主电极。

    Semiconductor device with trench gate
    37.
    发明授权
    Semiconductor device with trench gate 有权
    具有沟槽栅极的半导体器件

    公开(公告)号：US06747295B2

    公开(公告)日：2004-06-08

    申请号：US10345268

    申请日：2003-01-16

    申请人： Tomoki Inoue ,  Koichi Sugiyama ,  Hideaki Ninomiya ,  Tsuneo Ogura

    发明人： Tomoki Inoue ,  Koichi Sugiyama ,  Hideaki Ninomiya ,  Tsuneo Ogura

    IPC分类号： H01L2978

    CPC分类号： H01L29/66348 ,  H01L29/7397

    摘要： An IGBT has a p-emitter layer and p-base layer, which are arranged on both sides of an n-base layer. A pair of main trenches are formed to extend through the p-base layer and reach the n-base layer. In a current path region interposed between the main trenches, a pair of n-emitter layers are formed on the surface of the p-base layer. A narrowing trench is formed to extend through the p-base layer and reach the n-base layer. The narrowing trench narrows a hole flow path formed from the n-base layer to the emitter electrode through the p-base layer, thereby increasing the hole current resistance.

    摘要翻译： IGBT具有布置在n基层的两侧的p发射极层和p基极层。 一对主沟槽形成为延伸穿过p基层并到达n基层。 在介于主沟槽之间的电流路径区域中，在p基层的表面上形成一对n - 发射极层。 形成窄沟以延伸穿过p基层并到达n基层。 窄沟槽通过p基层使从n基层形成的空穴流路变窄到发射极，从而增加空穴电流电阻。

    Semiconductor device
    38.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06246077B1

    公开(公告)日：2001-06-12

    申请号：US09396372

    申请日：1999-09-15

    申请人： Setsuko Kobayashi ,  Takashi Shinohe ,  Tomoki Inoue ,  Akihiro Yahata

    发明人： Setsuko Kobayashi ,  Takashi Shinohe ,  Tomoki Inoue ,  Akihiro Yahata

    IPC分类号： H01L310312

    CPC分类号： H01L29/66068 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/7838

    摘要： A semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type formed on the surface of the first semiconductor layer, the energy difference between the bottom of the conductive band and the vacuum level in the second semiconductor layer being smaller than that in the first semiconductor layer, a gate electrode formed above the second semiconductor layer with a gate insulating film interposed therebetween, and a pair of third semiconductor layers of the second conductivity type, being in contact with at least the first semiconductor layer and faced each other in a region of the surface of the first semiconductor layer, so that a channel region is formed under the gate electrode.

    摘要翻译： 半导体器件包括第一导电类型的第一半导体层，形成在第一半导体层的表面上的第一导电类型的第二半导体层，导电带的底部与第二半导体层的真空度之间的能量差 半导体层比第一半导体层小的栅电极，形成在第二半导体层上方的栅极绝缘膜之间的栅电极和第二导电类型的一对第三半导体层与至少第一半导体层 半导体层并且在第一半导体层的表面的区域中彼此面对，从而在栅电极下形成沟道区。

    Semiconductor device
    39.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US5977564A

    公开(公告)日：1999-11-02

    申请号：US951674

    申请日：1997-10-16

    申请人： Setsuko Kobayashi ,  Takashi Shinohe ,  Tomoki Inoue ,  Akihiro Yahata

    发明人： Setsuko Kobayashi ,  Takashi Shinohe ,  Tomoki Inoue ,  Akihiro Yahata

    IPC分类号： H01L21/04 ,  H01L21/205 ,  H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/12 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78 ,  H01L31/0312

    CPC分类号： H01L29/66068 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/267 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/7838 ,  H01L29/1608

    摘要： A semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type formed on the surface of the first semiconductor layer, the energy difference between the bottom of the conductive band and the vacuum level in the second semiconductor layer being smaller than that in the first semiconductor layer, a gate electrode formed above the second semiconductor layer with a gate insulating film interposed therebetween, and a pair of third semiconductor layers of the second conductivity type, being in contact with at least the first semiconductor layer and faced each other in a region of the surface of the first semiconductor layer, so that a channel region is formed under the gate electrode.

    摘要翻译： 半导体器件包括第一导电类型的第一半导体层，形成在第一半导体层的表面上的第一导电类型的第二半导体层，导电带的底部与第二半导体层的真空度之间的能量差 半导体层比第一半导体层小的栅电极，形成在第二半导体层上方的栅极绝缘膜之间的栅电极和第二导电类型的一对第三半导体层与至少第一半导体层 半导体层并且在第一半导体层的表面的区域中彼此面对，从而在栅电极下形成沟道区。

    Solid-state imaging device including three stacked photoelectric conversion layers, three accumulators, and a single readout circuit
    40.
    发明授权
    Solid-state imaging device including three stacked photoelectric conversion layers, three accumulators, and a single readout circuit 失效
    固态成像装置包括三个堆叠的光电转换层，三个累加器和单个读出电路

    公开(公告)号：US07932942B2

    公开(公告)日：2011-04-26

    申请号：US11353236

    申请日：2006-02-14

    申请人： Tomoki Inoue ,  Atsuhiko Ishihara

    发明人： Tomoki Inoue ,  Atsuhiko Ishihara

    IPC分类号： H04N3/14 ,  H01L27/146

    CPC分类号： H04N9/045 ,  H04N2209/047

    摘要： A solid-state imaging device is provided and has: three photoelectric conversion layers stacked above a semiconductor substrate 1, each detecting a different color; three signal charge accumulators in a semiconductor substrate for accumulating signal charges generated in each of the three photoelectric conversion layers: and a signal readout circuit in the semiconductor substrate for reading out signals corresponding to the signal charges accumulated in the signal charge accumulators. The three signal charge accumulators are arranged in a direction in the surface of the semiconductor substrate as a pixel and a plurality of the pixels are arranged in a square lattice pattern both in the direction and a direction perpendicular thereto. The three signal charge accumulators arranged in each pixel in an odd row are arranged such that an array of the signal charge accumulators in the first sub-row of each pixel has all of the three signal charge accumulators.

    摘要翻译： 提供了一种固态成像装置，具有：叠层在半导体基板1上的三个光电转换层，每个检测不同的颜色; 用于累积在三个光电转换层中的每一个中产生的信号电荷的半导体衬底中的三个信号电荷累加器和用于读出与累积在信号电荷累加器中的信号电荷相对应的信号的半导体衬底中的信号读出电路。 三个信号电荷累积器沿着半导体衬底的表面的方向作为像素布置，并且多个像素在垂直于其的方向和方向上以正方形的格子图案排列。 布置在奇数行的每个像素中的三个信号电荷累加器布置成使得每个像素的第一子行中的信号电荷累加器的阵列具有三个信号电荷累加器的全部。