公开(公告)号：US20230101251A1

公开(公告)日：2023-03-30

申请号：US17947271

申请日：2022-09-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Akito MORI ,  Masahiro WAKASHIMA ,  Sho WATANABE ,  Takumi ENDOU

IPC: H01G4/30 ,  H01G4/12 ,  H01G4/008

Abstract: A multilayer ceramic capacitor includes a multilayer body including an inner layer portion including internal electrode layers and inner dielectric layers laminated alternately, and internal electrode layers at both ends thereof in a lamination direction, and outer dielectric layers covering the inner layer portion, and two external electrodes on both end surfaces of the multilayer body in a length direction intersecting the lamination direction. The inner and outer dielectric layers each include grains, and a difference between an average grain size of grains in the inner dielectric layers and an average grain size of grains in the outer dielectric layers is about 100 nm or less.

公开(公告)号：US20210202177A1

公开(公告)日：2021-07-01

申请号：US17131888

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta KUROSU ,  Yuta SAITO ,  Masahiro WAKASHIMA ,  Daiki FUKUNAGA ,  Yu TSUTSUI

IPC: H01G4/30 ,  H01G4/232 ,  H01G4/008 ,  H01G4/12 ,  H01G4/248

Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.

公开(公告)号：US20210202171A1

公开(公告)日：2021-07-01

申请号：US17131893

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yu TSUTSUI ,  Yuta KUROSU ,  Daiki FUKUNAGA ,  Yuta SAITO ,  Masahiro WAKASHIMA

IPC: H01G4/232 ,  H01G4/30 ,  H01G4/248 ,  H01G4/12

Abstract: A multilayer ceramic capacitor includes, in at least one of a region between an end of a first internal electrode layer which is not connected to a second external electrode and the second external electrode, and a region between an end of a second internal electrode layer which is not connected to a first external electrode and the first external electrode, in a length direction, a defect portion provided on a plane including a stacking direction and a width direction, such that the defect portion is located between the first dielectric ceramic layers in the stacking direction and is located between the second dielectric ceramic layer and the third dielectric ceramic layer in the width direction.

公开(公告)号：US20210098191A1

公开(公告)日：2021-04-01

申请号：US16988754

申请日：2020-08-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta SAITO ,  Akito MORI ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA

IPC: H01G4/232 ,  H01G4/30 ,  H01G4/12 ,  H01G4/008

Abstract: A multilayer ceramic capacitor includes a laminate including dielectric layers and internal electrode layers laminated together in a lamination direction, and a pair of external electrodes on both end surfaces of the laminate, the external electrodes being connected to the internal electrode layers, wherein a barrier is provided on a widthwise end of at least one internal electrode layer, the barrier having a thickness that decreases from the widthwise end of the internal electrode layer toward a side margin in a width direction, a void is defined by the widthwise end of the internal electrode layer, the barrier, and the side margin, and the barrier contains Ni and Sn.

公开(公告)号：US20200312561A1

公开(公告)日：2020-10-01

申请号：US16809614

申请日：2020-03-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masahiro WAKASHIMA

IPC: H01G4/232 ,  H01G4/30 ,  H01G4/12 ,  H01G4/008

Abstract: A multilayer ceramic capacitor includes a capacitive element including a ceramic layer, a first internal electrode layer, and a second internal electrode layer, the capacitive element including a first and second principal surfaces, first and second side surfaces, and first and second end surfaces. The first and second internal electrode layers respectively extend to the first and second end surfaces, at least a portion of each of the first and second end surfaces are covered with a conductor layer, a portion of the conductor layer is covered with an insulating portion, at least a portion of the conductor layer and at least a portion of the insulating portion are covered with the underlayer external electrode layer when viewed from the first end surface and the second end surface, and at least a portion of the underlayer external electrode layer is covered with a plating layer.

公开(公告)号：US20200066446A1

公开(公告)日：2020-02-27

申请号：US16547641

申请日：2019-08-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Daiki FUKUNAGA ,  Hideaki TANAKA ,  Masahiro WAKASHIMA ,  Daisuke HAMADA ,  Hironori TSUTSUMI ,  Satoshi MAENO ,  Ryota ASO ,  Koji MORIYAMA ,  Akihiro TSURU

IPC: H01G4/12 ,  H01G4/012 ,  H01G4/224 ,  H01G4/008 ,  H01G4/232

Abstract: An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction.

公开(公告)号：US20180042122A1

公开(公告)日：2018-02-08

申请号：US15669042

申请日：2017-08-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masahiro WAKASHIMA ,  Yuta SAITO ,  Kohei SHIMADA ,  Naobumi IKEGAMI

IPC: H05K3/34 ,  H01G4/12 ,  H01G4/005 ,  H05K1/02 ,  H01G2/06 ,  H05K1/18 ,  H01G4/232

CPC classification number: H05K3/3442 ,  H01G2/065 ,  H01G4/005 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30 ,  H01G4/38 ,  H01G4/40 ,  H05K1/0271 ,  H05K1/0295 ,  H05K1/181 ,  H05K2201/10015 ,  H05K2201/10522 ,  Y02P70/611

Abstract: An electronic component is able to be mounted on a mounting substrate on which a first electronic component and a second electronic component are able to be mounted. When dimensions of the first electronic component and the second electronic component in a width direction is designated as W1 and W2, respectively, and dimensions of the first electronic component and the second electronic component in a length direction are designated as L1 and L2, respectively, dimensions of the electronic component in the width direction and the length direction are any one of combinations of W1 and L2, and of W2 and L1. The electronic component includes a third laminate including a pair of third principal surfaces, a pair of third side surfaces, and a pair of third end surfaces, and a pair of third external electrodes. Each of the pair of third external electrodes includes a fired layer, and a resin layer provided on an external surface of the fired layer. On each of the pair of third principal surfaces and on each of the pair of third side surfaces, a length of the resin layer along the length direction from a corresponding one of the third end surfaces to a leading end of the resin layer is less than a length of the fired layer along the length direction from a corresponding one of the third end surfaces to a leading end of the fired layer.