公开(公告)号：US08183114B2

公开(公告)日：2012-05-22

申请号：US12636408

申请日：2009-12-11

申请人： Nobuo Tsuboi ,  Motoshige Igarashi

发明人： Nobuo Tsuboi ,  Motoshige Igarashi

IPC分类号： H01L21/00

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.

摘要翻译： 采用在栅极2a和栅极2b之间提供局部布线3a并连接有源区域1a和有源区域1b的SRAM单元布局的结构。 这消除了在栅极2a和栅极2b之间提供接触的必要性。 因此，可以在短边方向上减小存储单元区域C的尺寸。 此外，采用栅极2c的左端从栅极2a退出的结构和连接沿对角线方向设置的有源区域1b和栅极2c的局部布线3b。 这允许栅极2a朝向存储单元区域C的中心移动。

公开(公告)号：US08089136B2

公开(公告)日：2012-01-03

申请号：US12891214

申请日：2010-09-27

申请人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

发明人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

IPC分类号： H01L29/00

CPC分类号： H01L27/0207 ,  H01L27/0629 ,  H01L27/0802 ,  H01L28/20

摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

摘要翻译： 本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。 有源区靠近电阻元件配置。 这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。

公开(公告)号：US07663193B2

公开(公告)日：2010-02-16

申请号：US12237693

申请日：2008-09-25

申请人： Nobuo Tsuboi ,  Motoshige Igarashi

发明人： Nobuo Tsuboi ,  Motoshige Igarashi

IPC分类号： H01L21/00

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.

摘要翻译： 采用在栅极2a和栅极2b之间提供局部布线3a并连接有源区域1a和有源区域1b的SRAM单元布局的结构。 这消除了在栅极2a和栅极2b之间提供接触的必要性。 因此，可以在短边方向上减小存储单元区域C的尺寸。 此外，采用栅极2c的左端从栅极2a退出的结构和连接沿对角线方向设置的有源区域1b和栅极2c的局部布线3b。 这允许栅极2a朝向存储单元区域C的中心移动。

公开(公告)号：US20090026520A1

公开(公告)日：2009-01-29

申请号：US12237693

申请日：2008-09-25

申请人： Nobuo TSUBOI ,  Motoshige Igarashi

发明人： Nobuo TSUBOI ,  Motoshige Igarashi

IPC分类号： H01L47/00

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.

摘要翻译： 采用在栅极2a和栅极2b之间提供局部布线3a并连接有源区域1a和有源区域1b的SRAM单元布局的结构。 这消除了在栅极2a和栅极2b之间提供接触的必要性。 因此，可以在短边方向上减小存储单元区域C的尺寸。 此外，采用栅极2c的左端从栅极2a退出的结构和连接沿对角线方向设置的有源区域1b和栅极2c的局部布线3b。 这允许栅极2a朝向存储单元区域C的中心移动。

公开(公告)号：US20060175679A1

公开(公告)日：2006-08-10

申请号：US11384244

申请日：2006-03-21

申请人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

发明人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

IPC分类号： H01L29/00

CPC分类号： H01L27/0207 ,  H01L27/0629 ,  H01L27/0802 ,  H01L28/20

摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

公开(公告)号：US07045865B2

公开(公告)日：2006-05-16

申请号：US09960495

申请日：2001-09-24

申请人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

发明人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

IPC分类号： H01L29/76 ,  H01L29/00 ,  H01L21/20

CPC分类号： H01L27/0207 ,  H01L27/0629 ,  H01L27/0802 ,  H01L28/20

摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

摘要翻译： 本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。 有源区靠近电阻元件配置。 这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。

公开(公告)号：US20050112832A1

公开(公告)日：2005-05-26

申请号：US10982903

申请日：2004-11-08

申请人： Hiroshi Kawashima ,  Motoshige Igarashi ,  Keiichi Higashitani

发明人： Hiroshi Kawashima ,  Motoshige Igarashi ,  Keiichi Higashitani

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H01L21/336 ,  H01L21/04 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L27/0629 ,  H01L28/20

摘要： A thermal process for activating respective impurities in a polysilicon film to be a gate electrode and a resistance element is performed with the polysilicon film to be the gate electrode and the resistance element being coated with an oxide film, after the respective impurities are implanted into the polysilicon film to be the gate electrode and the resistance element. Here, concentrations of the respective impurities in the polysilicon film to be the gate electrode and the resistance element are adjusted by controlling the thickness of the oxide film. The degree of impurity activation is thereby adjusted.

公开(公告)号：US06841459B2

公开(公告)日：2005-01-11

申请号：US10288458

申请日：2002-11-06

申请人： Hiroshi Kawashima ,  Motoshige Igarashi ,  Keiichi Higashitani

发明人： Hiroshi Kawashima ,  Motoshige Igarashi ,  Keiichi Higashitani

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H01L21/04 ,  H01L21/336

CPC分类号： H01L28/20 ,  H01L21/26513 ,  H01L21/324 ,  H01L27/0629

摘要： A thermal process for activating respective impurities in a polysilicon film to be a gate electrode and a resistance element is performed with the polysilicon film to be the gate electrode and the resistance element being coated with an oxide film, after the respective impurities are implanted into the polysilicon film to be the gate electrode and the resistance element. Here, concentrations of the respective impurities in the polysilicon film to be the gate electrode and the resistance element are adjusted by controlling the thickness of the oxide film. The degree of impurity activation is thereby adjusted.

摘要翻译： 在将各种杂质植入到所述多晶硅膜中之后，在多晶硅膜中激活作为栅电极和电阻元件的各杂质的热处理被执行，所述多晶硅膜为栅电极，电阻元件涂覆有氧化物膜 多晶硅膜是栅电极和电阻元件。 这里，通过控制氧化膜的厚度来调节作为栅电极和电阻元件的多晶硅膜中各杂质的浓度。 从而调节杂质活化程度。

公开(公告)号：US06838732B2

公开(公告)日：2005-01-04

申请号：US09971958

申请日：2001-10-09

申请人： Motoshige Igarashi ,  Hiroyuki Amishiro

发明人： Motoshige Igarashi ,  Hiroyuki Amishiro

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8244 ,  H01L23/522 ,  H01L27/088 ,  H01L27/11 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823468 ,  H01L23/5222 ,  H01L29/6653 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor device with reduced parasitic capacity in the vicinity of gate electrodes, and a method for manufacturing such a semiconductor device. The semiconductor device comprises a gate electrode formed on a silicon semiconductor substrate 1 through a gate oxide film, and a pair of impurity diffusion layers formed on the surface region of the silicon semiconductor substrate at both sides of the gate electrode. A silicon nitride film acting as a sidewall spacer is formed so as to cover the sidewall of the gate electrode, and the silicon nitride film is allowed to extend to the surface of the silicon semiconductor substrate 1 in the vicinity of the gate electrode in a substantially L-shaped profile.

摘要翻译： 提供在栅极附近具有降低的寄生电容的半导体器件，以及制造这种半导体器件的方法。 半导体器件包括通过栅极氧化膜形成在硅半导体衬底1上的栅极电极和形成在栅极电极两侧的硅半导体衬底的表面区域上的一对杂质扩散层。 形成作为侧壁间隔物的氮化硅膜，以覆盖栅电极的侧壁，并且允许氮化硅膜基本上在栅电极附近延伸到硅半导体衬底1的表面 L型轮廓。

公开(公告)号：US06815839B2

公开(公告)日：2004-11-09

申请号：US10668330

申请日：2003-09-24

申请人： Koji Nii ,  Motoshige Igarashi

发明人： Koji Nii ,  Motoshige Igarashi

IPC分类号： H01L2711

CPC分类号： G11C11/412 ,  Y10S257/903 ,  Y10S257/904

摘要： The semiconductor memory device includes two PMOS transistors that make the SRAM memory cell. The gate insulating films of these PMOS transistors are formed using a material that has a high permittivity. As a result, the capacitance of memory nodes is increased, and the probability of soft errors is lowered.

摘要翻译： 半导体存储器件包括制造SRAM存储单元的两个PMOS晶体管。 这些PMOS晶体管的栅极绝缘膜使用具有高介电常数的材料形成。 结果，存储器节点的电容增加，并且软错误的概率降低。